EM78P447S
OTP ROM
Aaddress
R PAGE registers
IOC PAGE registers
R0
R1
R2
R3
R4
R5
R6
R7
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
(Indirect Addressing Register)
(Time Clock Counter)
(Program Counter)
(Status Register)
(RAM Select Register)
(Port5)
Reserve
(Control Register)
Reserve
CONT
Reserve
Reserve
IOC5
IOC6
IOC7
(I/O Port Control Register)
(I/O Port Control Register)
(I/O Port Control Register)
Reserve
(Port6)
(Port7)
General Register
General Register
General Register
General Register
General Register
General Register
General Register
General Register
Reserve
Reserve
IOCB
(Wake-Up Control Register for Port6 )
Reverse
Reverse
(WDT,SLEEP2,Open Drain,R -Option
Control Register)
IOCE
IOCF
(Interrupt Mask Register)
10
︰
1F
General Registers
20
：
3E
Bank0
Bank1
Bank2
Bank3
R3F
3F
(Interrupt Status Register)
Fig. 4 Data Memory Configuration
This specification is subject to change without prior notice.
10
06.25.2003 (V1.1)
ELAN [ ELAN MICROELECTRONICS CORP ]
