EM78P417N/418N/419N
8-Bit Microprocessor with OTP ROM
Bit 2 ~ 0 (PR2 ~ PR0):
Protect Bit
PR2 ~ PR0 are protect bits. Each protect status is as
follows:
PR2
PR1
PR0
Protect
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Disable
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
6.13.2 Code Option Register (Word 1)
WORD 1
Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
–
–
–
–
NRHL NRE CYES
C3
C2
C1
C0
RCM1 RCM0
Bits 12 ~ 9:
Not used (reserved). These bits are set to “1” all the time
Bit 8 (NRHL):
Noise rejection high/low pulses define bit. INT pin is falling edge
trigger
0 = Pulses equal to 8/fc [s] is regarded as signal.
1 = Pulses equal to 32/fc [s] is regarded as signal.
(default)
NOTE
The noise rejection function is turned off under the LXT and sleep mode.
Bit 7 (NRE):
Noise rejection enable
0 = disable noise rejection
1 = enable noise rejection (default). However under Low XTAL
oscillator (LXT) mode, the noise rejection circuit always
disabled.
Bit 6 (CYES):
Instruction cycle selection bit
0 = one instruction cycle
1 = two instruction cycles (default)
Bits 5, 4, 3 & Bit2 ( C3, C2, C1, & C0 ): Calibrator of internal RC mode. These bits
must always be set to “1” only (auto calibration)
Product Specification (V1.0) 06.23.2005
• 63
(This specification is subject to change without further notice)
ELAN [ ELAN MICROELECTRONICS CORP ]
