EM78P350N
8-Bit Microprocessor with OTP ROM
Example: Idle mode: IDLE bit = “0” + SLEP instruction + NOP instruction
Sleep mode: IDLE bit = ”1” + SLEP instruction + NOP instruction.
Only the normal can entering sleep mode, idle mode can’t entering the sleep mode.
Wake-up
Wake-up
All wake-up function
except PWM
Pin change or Timer
interrupt or AD or
comparator
Normal Mode
IDLE = "0"+SLEP
Timer must
select low
IDLE = "1"+SLEP
crystal source
in normal mode
Idle Mode
Sleep Mode
Fig 6-4 CPU Operation Mode
In Sleep mode, the internal oscillator is turned off and all system operation is halted.
Sleep mode is released by /Sleep pin (level sensitive or edge sensitive). After warm-up
period, the next instruction will be executed which is after the Sleep mode start
instruction. Sleep mode can also be released by setting the /Reset pin to low and
executing a reset operation.
In Idle mode, only the low crystal source existence, the others crystal source were off.
Only the Timer (TCC, Timer 1, Timer 2, Timer 3, PWM1, PWM2, PWM3) can work
normally when its clock source select low crystal (if clock source select High crystal,
timer will not work). If timer set the PWMWE as “1”, when the timer or PWM occurs
interrupt will wake up the CPU and entering normal mode. The TCC overflow will not
wake up CPU.
6.1.28 Bank 2 R8 (AISR: ADC Input Select Register)
The AISR register defines the pins of Port 6 as analog inputs or as digital I/O,
individually.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ADE7
ADE6
ADE5
ADE4
ADE3
ADE2
ADE1
ADE0
Bit 7 (ADE7): AD converter enable bit of P67 pin
0 = Disable AIN7, P67 functions as I/O pin
1 = Enable AIN7, to function as analog input pin
Bit 6 (ADE6): AD converter enable bit of P66 pin
0 = Disable AIN6, P66 functions as I/O pin
1 = Enable AIN6, to function as analog input pin
20 •
Product Specification (V1.0) 09.14.2006
(This specification is subject to change without further notice)
ELAN [ ELAN MICROELECTRONICS CORP ]
