EM78P350N
8-Bit Microprocessor with OTP ROM
6.1.21 Bank1 RB (PRDL: Least Significant Bits of PWM Period
Cycle)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
“0”
“0”
PRD3[1] PRD3[0] PRD2[1]
PRD2[0]
PRD1[1] PRD1[0]
Bit 7 & Bit 6: Unimplemented, read as ‘0’.
Bit 5 & Bit 4 (PRD3[1], PRD3[0]): Least Significant Bits of PWM3 Period Cycle.
Bit 3 & Bit 2 (PRD2[1], PRD2[0]): Least Significant Bits of PWM2 Period Cycle.
Sectioning actions refer to the Reset description. The following actions refer to the
section status operation.
Bit 1 & Bit 0 (PRD1[1], PRD1[0]): Least Significant Bits of PWM1 Period Cycle.
6.1.22 Bank 1 RC (DT1H: Most Significant Byte (Bit 9 ~ Bit 2) of
PWM1 Duty Cycle)
Aspecified value keeps the output of PWM1 to remain high until the value matches with
TMR1.
6.1.23 Bank 1 RD (DT2H: Most Significant Byte (Bit 9 ~ Bit 2) of
PWM2 Duty Cycle)
Aspecified value keeps the output of PWM2 to remain high until the value matches with
TMR2.
6.1.24 Bank1 RE (DT3H: Most Significant Byte (Bit 9 ~ Bit 2) of
PWM3 Duty Cycle)
Aspecified value keeps the output of PWM3 to remain high until the value matches with
TMR3.
6.1.25 Bank1 RF (DTL: Least Significant Bits of PWM Duty Cycle)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
“0”
“0”
PWM3[1] PWM3[0] PWM2[1] PWM2[0] PWM1[1] PWM1[0]
Bit 7 & Bit 6: Unimplemented, read as ‘0’
Bit 5 & Bit 4 (PWM3[1], PWM3[0]): Least Significant Bits of PWM3 Duty Cycle
Bit 3 & Bit 2 (PWM2[1], PWM2[0]): Least Significant Bits of PWM2 Duty Cycle
Bit 1 & Bit 0 (PWM1[1], PWM1[0]): Least Significant Bits of PWM1 Duty Cycle
Product Specification (V 1.0) 09.14.2006
(This specification is subject to change without further notice)
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ELAN [ ELAN MICROELECTRONICS CORP ]
