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EM78P259NSO14J 参数 Datasheet PDF下载

EM78P259NSO14J图片预览
型号: EM78P259NSO14J
PDF下载: 下载PDF文件 查看货源
内容描述: [EM78Q153SN EM78P153SP EM78P153SN EM78156EH EM78156EP EM78156EM EM78156EKM EM78Q156ELP EM78Q156ELM EM78Q156ELKM EM78P156ELP EM78P156ELM EM78P156ELKM EM78P156NP EM78P156NM EM78447SH EM78447SAP EM78447SAM EM78447SAS EM78447SBP EM78447SBWM EM78Q447SH EM78Q447SAP EM78Q447SAM EM78Q447SBP EM78Q447SBWM EM78P447SAP EM78P447SAM EM78P447SAS EM78P447SBP EM78P447SBWM EM78Q257 EM78Q257AP EM78Q257AM EM78Q257BP EM78Q257BM EM78P257AP EM78P257AM EM78P257BP EM78P257BM EM78451H EM78451P EM78451AQ EM]
分类和应用:
文件页数/大小: 81 页 / 2574 K
品牌: ELAN [ ELAN MICROELECTRONICS CORP ]
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EM78P258N  
8-Bit Microprocessor with OTP ROM  
6.9 Timer / Counter  
6.9.1 Overview  
TimerA (TCCA ) is an 8-bit clock counters. TimerB (TCCB) is a 16-bit clock counter.  
TimerC (TCCC) is an 8-bit clock counters that can be extended to 16-bit clock counter  
with programmable scalers. TCCA, TCCB, and TCCC can be read and written; and are  
cleared at every reset condition.  
6.9.2 Function Description  
Set predict value  
Set predict value  
Set predict value  
TCCCEN  
Set TCCCIF  
TCCAEN  
TCCBEN  
Set TCCBIF  
Set TCCAIF  
TCCC  
TCCB  
TCCA  
Overflow  
TCCCS1 ~ TCCCS0  
Overflow  
Overflow  
System clock  
System clock or  
External input  
8-to-1 MUX  
8 Bit  
counter  
System clock  
Fig. 6.12 TIMER Block Diagram  
Each signal and block of the above TIMER block diagram is described as follows:  
TCCX: Timer A~C register. TCCX increases until it matches with zero, and then  
reload the predicted value. When writing a value to TCCX, the predicted value  
and TCCX value become the set value. When reading from TCCX, the value  
will be the TCCX direct value. When TCCXEN is enabled, the reload of the  
predicted value to TCCX, TCCXIE is also enabled. TCCXIF will be set at the  
same time. It is an up counter.  
Under TCCA Counter (IOC51):  
IOC51 (TCCA) is an 8-bit clock counter. It can be read, written, and cleared on  
any reset condition and is an UP Counter.  
NOTE  
TCCA timeout period [1/Fosc x (256-TCCA cnt) x 1(CLK=2)]  
TCCA timeout period [1/Fosc x (256-TCCA cnt) x 2(CLK=4)]  
Under TCCB Counter (IOC61):  
An 8-bit clock counter is for the least significant byte of TCCBX (TCCB). It can  
be read, written, and cleared on any reset condition and is an UP Counter.  
Product Specification (V1.0) 06.16.2005  
53  
(This specification is subject to change without further notice)  
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