EM78P258N
8-Bit Microprocessor with OTP ROM
Bit 3 (TCCAIE): TCCAIF interrupt enable bit
0 = Disable TCCAIF interrupt
1 = Enable TCCAIF interrupt
Bit 2 (EXIE):
Bit 1 (ICIE):
Bit 0 (TCIE):
EXIF interrupt enable bit
0 = Disable EXIF interrupt
1 = Enable EXIF interrupt
ICIF interrupt enable bit
0 = Disable ICIF interrupt
1 = Enable ICIF interrupt
TCIF interrupt enable bit.
0 = Disable TCIF interrupt
1 = Enable TCIF interrupt
6.2.12 IOC51 (TCCA Counter)
IOC51 (TCCA) is an 8-bit clock counter. It can be read, written, and cleared on any
reset condition and is an UP Counter.
NOTE
■ TCCA timeout period [1/Fosc x (256-TCCA cnt) x 1(CLK=2)]
■ TCCA timeout period [1/Fosc x (256-TCCA cnt) x 2(CLK=4)]
6.2.13 IOC61 (TCCB Counter)
An 8-bit clock counter is for the least significant byte of TCCBX (TCCB). It can be read,
written, and cleared on any reset condition and is an UP Counter.
6.2.14 IOC71 (TCCBH / MSB Counter)
An 8-bit clock counter is for the most significant byte of TCCBX (TCCBH). It can be
read, written, and cleared on any reset condition.
When TCCBHE (IOC90) is “0,” then TCCBH is disabled. When TCCBHE is”1,” then
TCCB is a 16-bit length counter.
NOTE
When TCCBH is Disabled:
■ TCCB timeout period [1/Fosc x ( 256 - TCCB cnt ) x 1(CLK=2)]
■ TCCB timeout period [1/Fosc x ( 256 - TCCB cnt ) x 2(CLK=4)]
When TCCBH is Enabled:
■ TCCB timeout period {1/Fosc x [ 65536 - (TCCBH * 256 + TCCB cnt)] x 1(CLK=2)}
■ TCCB timeout period {1/Fosc x [ 65536 - (TCCBH * 256 + TCCB cnt)] x 2(CLK=4)}
22 •
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
ELAN [ ELAN MICROELECTRONICS CORP ]
