EM78P257
OTP ROM
PCRD
P
Q
R
D
CLK
_
Q
PCWR
C
L
P50 ~ P57
PORT
P
R
IOD
Q
D
CLK
_
Q
PDWR
C
L
M
U
X
0
1
PDRD
TI n
P
R
D
Q
CLK
_
Q
C
L
NOTE: Pull-high(down) is not shown in the figure.
Fig. 9 The Circuit of I/O Port and I/O Control Register for P50~P57
IOCF. 1
RF.1
TI
TI
0
1
TI
8
Fig. 10 Block Diagram of I/O Port 5 with Input Change Interrupt/Wake-up
This specification is subject to change without prior notice.
31
07.27.2004 (V1.4)