EM78P257
OTP ROM
PCRD
P
Q
D
R
PCWR
CLK
_
Q
C
L
P
IOD
PORT
Q
D
R
PDWR
CLK
_
Q
C
L
PDRD
0
1
M
U
X
NOTE: Open-drain is not shown in the figure.
Fig. 7 The circuit of I/O port and I/O control register for Port 6 and Port7
PCRD
P
Q
_
Q
D
R
CLK
P C W R
P D W R
C
L
IOD
P
Q
_
Q
PORT
D
R
CLK
C
Bit 6 of IOCE
L
0
1
P
D
Q
M
U
X
R
_
Q
CLK
C
L
T10
PDRD
P
D
Q
R
CLK
_
Q
C
L
NOTE: Open-drain is not shown in the figure.
Fig. 8 The Circuit of I/O Port and I/O Control Register for P60(/INT)
This specification is subject to change without prior notice.
30
07.27.2004 (V1.4)