EM78P257
OTP ROM
4. FUNCTION DESCRIPTION
ROM
STACK 0
/INT
R2
TCC
WDT timer
OSCO
STACK 1
STACK 2
/RESET
OSCI
STACK 3
STACK 4
Oscillator Timing
Control
Prescaler
STACK 5
STACK 6
Interrupt
controller
Instruction
Register
STACK 7
RAM
R4
ALU
Built-in
OSC
R1(TCC)
Instruction
decoder
R3
ACC
DATA & CONTROL BUS
P60/INT
TCC4/CIN1+/P50
P61/CIN3-/TCC1
P62/CIN3+
P63/CO3
TCC3/CO1/P51
CO2/P52
Comparator COUNTER
IOC5
IOC6/7
I/O
PORT5
CIN2+/P53
I/O
PORT6/7
P64/CO4
TCC/CIN2-/P54
OSCI/CIN1-/P55
TCC5/P56
P65/CIN4+
P66/CIN4-/TCC2
P67/IR OUT
P70/OSCO
R6/7
R5
TCC6/P57
P71//RESET
Fig. 3 Functional block diagram
4.1 Operational Registers
1. R0 (Indirect Addressing Register)
R0 is not a physically implemented register. Its major function is to be an indirect addressing pointer. Any instruction using
R0 as a pointer actually accesses data pointed by the RAM Select Register (R4).
2. R1 (Time Clock /Counter)/TCC
• Increased by an external signal edge which is defined by the TE bit (CONT-4) through the TCC pin,
or by the instruction cycle clock.
• Writable and readable as any other registers.
• The prescaler (RC) is assigned to TCC.
• The contents of the prescaler counter is cleared only when a value is written to TCC register.
3. R2 (Program Counter) & Stack/PC
This specification is subject to change without prior notice.
10
07.27.2004 (V1.4)
ELAN [ ELAN MICROELECTRONICS CORP ]
