EM78815
8-Bit Microcontroller
6.5 DTMF Receiver, OP
Pin
I/O
Description
Early steering output. Presents a logic high immediately
when the digital algorithm detects a recognizable tone-pair
(signal condition). Any momentary loss of signal condition
will cause the EST to return to a logic low. This is pin-
shared with Port 61.
EST
O
Steering input/guard time output (bi-directional). A voltage
greater than Vtst detected at ST causes the device to
register the detected tone-pair and update the output latch.
A voltage less than Vtst frees the device to accept a new
tone-pair. The GT output acts to reset the external steering
time-constant; its state is a function of EST and the voltage
on ST. This is pin-shared with Port 60.
STGT
I/O
6.6 Serial IO, Comparator, Current DA, Tone
Pin
I/O
Description
Master: output pin, Slave: input pin. This is pin-shared with
Port D4.
SCK
I/O
Output pin for serial data transferring. This is pin-shared with
Port D5.
SDO
O
SDI
UR
UT
CMP1
CMP2
CMP3
I
I
O
I
I
I
Input pin for receiving data. This is pin-shared with Port D6.
Data receiver pin for UART. This pin shared with Port D2
Data transmitter pin for UART. This is pin-shared with Port D3.
Comparator input pins. This is pin-shared with Port 65.
Comparator input pins. This is pin-shared with Port 66
Comparator input pins. This is pin-shared with Port 67.
Current DA output pin. It can be a control signal for sound
generation. This is pin-shared with Port D7.
Key tone output. This is pin-shared with Port 76.
Dual tone output pin
DAOUT
O
KTONE
TONE
O
O
6.7 IO
Pin
I/O
Description
Each bit in Port 6 can be Input or Output port.
Internal pull high.
P60 ~P67
I/O
Each bit in Port 7 can be Input or Output port.
Internal Pull high function, Auto key scan function, and
Interrupt function.
P70 ~ P77
I/O
P80 ~ P87
P90 ~ P97
PB0 ~ PB7
PC0 ~ PC7
I/O
I/O
I/O
I/O
Each bit in Port 8 can be Input or Output port.
Each bit in Port 9 can be Input or Output port.
Each bit in Port B can be Input or Output port.
Each bit in Port C can be Input or Output port.
Each bit in Port D can be Input or Output port.
This is pin-shared with SPI pin and CMP input pin.
Interrupt sources. When any pin from Port 70 to Port 76
has a falling edge signal, it will generate a corresponding
interrupt.
PD0 ~ PD7
I/O
P70 ~ P76
I
Interrupt source. Once Port 77 has a falling edge or rising
edge signal (controlled by CONT register), it will generate
an interrupt.
P77
I
I
/RESET
Low reset
8 •
Product Specification (V2.4) 02.17.2006
(This specification is subject to change without further notice)
ELAN [ ELAN MICROELECTRONICS CORP ]
