EM78815
8-Bit Microcontroller
7.3.11.2 Page 1 Port 7 Pull High Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PH77
PH76
PH75
PH74
PH73
PH72
PH71
PH70
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Bit 0~Bit 7(PH70~PH77) : Port 7(0~7) pull high control register
0 → disable pull-high function
1 → enable pull-high function
7.3.12 IOCE Interrupt Mask, Differential Energy Detect
7.3.12.1 Page 0 Interrupt Mask Register 1
Bit 7
INT7
Bit 6
INT6
Bit 5
INT5
Bit 4
INT4
Bit 3
INT3
Bit 2
INT2
Bit 1
INT1
Bit 0
INT0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Bit 0~Bit 7 :
Interrupt enable bits
0/1 → disable interrupt/enable interrupt
7.3.12.2 Page 1 Differential Energy Detect
Bit 7
VRSEL
R/W-0
Bit 6
DEDD
R
Bit 5
EDGE
R/W-0
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WUEDD CW_SMB DEDCLK DEDPWR DEDTHD
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
Bit 0 (DEDTHD) : Minimum detection threshold for Differential Energy Detector (DED)
0/1 → -45dBm/-30dBm
Bit 1 (DEDPWR) : Power control of Differential Energy Detector (DED)
0/1 → Power off / Power on
Bit 2 (DEDCLK) : Operating clock for Differential Energy Detector (DED)
0/1 → 32.768kHz/3.5826 MHz
This bit is used to select operating clock for the Differential Energy Detector (DED).
When this bit is set to “1”, the PLL is also enabled regardless of RA Bit 6 (ENPLL).
During this time, the Energy detector works at high frequency mode. When this bit is
set to “0”, the Energy Detector works at a low frequency mode. The difference
between high frequency and low frequency is as follows.
DEDPWR
DEDCLK
ENPLL
Energy Detector Clock
×
Main CLK
Determined by ENPLL
Disable
0
1
1
1
1
×
0
0
1
1
×
0
1
0
1
32.768 kHz
32.768 kHz
3.5826 MHz
3.5826 MHz
Enable
Enable
Enable
Note: ”×” means don’t care
Product Specification (V2.4) 08.01.2004
(This specification is subject to change without further notice)
57
ELAN [ ELAN MICROELECTRONICS CORP ]
