EM78468
8-BIT Microcontroller
INSTRUCTION
BINARY
STATUS
HEX
MNEMONIC
OPERATION
AFFECTED
0 0000 0000 0000 0000 NOP
0 0000 0000 0001 0001 DAA
0 0000 0000 0011 0003 SLEP
0 0000 0000 0100 0004 WDTC
No Operation
None
Decimal Adjust A
C
T, P
T, P
0 → WDT, Stop oscillator
0 → WDT
A → IOCR
0 0000 0000 rrrr
000r
IOW
R
None <Note1>
None
None
None
0 0000 0001 0000 0010 ENI
0 0000 0001 0001 0011 DISI
0 0000 0001 0010 0012 RET
Enable Interrupt
Disable Interrupt
[Top of Stack] → PC
[Top of Stack] → PC,
Enable Interrupt
IOCR → A
0 0000 0001 0011 0013 RETI
None
0 0000 0001 rrrr
0 0000 01rr rrrr
0 0000 1000 0000 0080 CLRA
001r
00rr
IOR
MOV
R
R, A
None <Note1>
None
A → R
Z
Z
0 → A
0 0000 11rr rrrr
0 0001 00rr rrrr
0 0001 01rr rrrr
0 0001 10rr rrrr
0 0001 11rr rrrr
0 0010 00rr rrrr
0 0010 01rr rrrr
0 0010 10rr rrrr
0 0010 11rr rrrr
0 0011 00rr rrrr
0 0011 01rr rrrr
0 0011 10rr rrrr
0 0011 11rr rrrr
0 0100 00rr rrrr
0 0100 01rr rrrr
0 0100 10rr rrrr
0 0100 11rr rrrr
0 0101 00rr rrrr
0 0101 01rr rrrr
0 0101 10rr rrrr
0 0101 11rr rrrr
00rr
01rr
01rr
01rr
01rr
02rr
02rr
02rr
02rr
03rr
03rr
03rr
03rr
04rr
04rr
04rr
04rr
05rr
05rr
05rr
05rr
CLR
SUB
SUB
DECA
DEC
OR
R
0 → R
A, R
R, A
R
Z, C, DC
Z, C, DC
R-A → A
R-A → R
Z
R-1 → A
R
Z
R-1 → R
A, R
R, A
A, R
R, A
A, R
R, A
A, R
R, A
A, R
R, R
R
Z
A ∨ R → A
A ∨ R → R
A & R → A
A & R → R
A ⊕ R → A
A ⊕ R → R
A + R → A
A + R → R
R → A
OR
Z
AND
AND
XOR
XOR
ADD
ADD
MOV
MOV
COMA
COM
INCA
INC
Z
Z
Z
Z
Z, C, DC
Z, C, DC
Z
Z
R → R
Z
/R → A
R
Z
/R → R
R
Z
R+1 → A
R+1 → R
R-1 → A, skip if zero
R
Z
DJZA
DJZ
R
None
None
R
R-1 → R, skip if zero
R(n) ( A(n-1),
0 0110 00rr rrrr
0 0110 01rr rrrr
0 0110 10rr rrrr
0 0110 11rr rrrr
0 0111 00rr rrrr
06rr
06rr
06rr
06rr
07rr
RRCA
R
R
R
R
C
R(0) ( C, C ( A(7)
R(n) ( R(n-1),
RRC
C
R(0) ( C, C ( R(7)
R(n) ( A(n+1),
RLCA
RLC
C
R(7) ( C, C ( A(0)
R(n) ( R(n+1),
R(7) ( C, C ( R(0)
R(0-3) ( A(4-7),
R(4-7) ( A(0-3)
R(0-3) ( R(4-7)
R+1 ( A, skip if zero
R+1 ( R, skip if zero
0 ( R(b)
C
SWAPA R
None
0 0111 01rr rrrr
0 0111 10rr rrrr
0 0111 11rr rrrr
0 100b bbrr rrrr
0 101b bbrr rrrr
07rr
07rr
07rr
0xxx BC
0xxx BS
SWAP
JZA
JZ
R
None
None
None
None
None
R
R
R, b
R, b
1 ( R(b)
54 •
Product Specification (V1.1) 04.11.2005
(This specification is subject to change without further notice)