EM78468
8-BIT Microcontroller
prescaler * (preset _ value +1)
FT
Low pulse time =
4.2.12 IOCF0/IMR (Interrupt Mask Register)
(Address: 0Fh, Bit 0 of R5 = “0”)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ICIE
LPWTE HPWTE CNT2E
CNT1E
INT1E
INT0E
TCIE
Bit 7~Bit 0: interrupt enable bit. Enable interrupt source respectively.
0: disable interrupt
1: enable interrupt
IOCF0 register is readable and writable.
Registers of IOC Page 1 (IOC61 ~ IOCE1, Bit 0 of R5 = “1”)
4.2.13 IOC61/WUCR (Wake Up and sink current of P5.7/IROUT Control
Register)
(Address: 06h, Bit 0 of R5 = “1”)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
IROCS
--
--
--
/WUE8H /WUE8L /WUE6H /WUE6L
Bit 7: IROCS: IROUT/PORT5.7 output sink current set
P5.7/IROUT Sink current
IROCS
VDD=5V
VDD=3V
0
1
9 mA
18 mA
6 mA
12 mA
Bit 6,5,4: Not used
Bit 3 (/WUE8H): 0/1=> enable/disable P8.4~P8.7 pin change wake up function
Bit 2 (/WUE8L): 0/1=> enable/disable P8.0~P8.3 pin change wake up function
Bit 1 (/WUE6H): 0/1=> enable/disable P6.4~P6.7 pin change wake up function
Bit 0 (/WUE6L): 0/1=> enable/disable P6.0~P6.3 pin change wake up function
Port 6 and Port 8 must avoid input floating when wakeup function is enabled.
The initial state of wakeup function is enabled.
4.2.14 IOC71/TCCCR (TCC Control Register)
(Address: 07h, Bit 0 of R5 = “1”)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INT_EDGE
INT
TS
TE
PSRE
TCCP2 TCCP1 TCCP0
Bit 7 (INT_EDGE):
INT_EDGE = ”0”: Interrupt on rising edge of P5.4/INT0 pin
22 •
Product Specification (V1.1) 04.11.2005
(This specification is subject to change without further notice)
ELAN [ ELAN MICROELECTRONICS CORP ]
