Contents
8.2.7 RX FIFO..........................................................................................................46
8.2.8 TX FIFO ..........................................................................................................47
8.2.9 Interrupt Driver ................................................................................................47
8.2.10 Packet Size .....................................................................................................49
8.2.11 NET_ID and NODE_ID Filters.........................................................................49
8.2.12 Carrier-Sense..................................................................................................50
8.2.12.1 RFWaves Carrier-Sense Algorithm...................................................50
8.2.13 Receiver Reference Capacitor Discharge .......................................................51
8.2.14 Changing BB Configuration.............................................................................52
8.2.15 Input Synchronizer ..........................................................................................52
8.3 Register Description .......................................................................................52
8.3.1 Bit Length Register (BLR) ...............................................................................53
8.3.2 Preamble Low Register (PRE-L) .....................................................................53
8.3.3 Preamble High Register (PRE-H)....................................................................53
8.3.4 Packet Parameter Register (PPR)...................................................................53
8.3.5 System Control Register1 (SCR1)...................................................................55
8.3.6 System Control Register 2 (SCR2)..................................................................55
8.3.7 System Control Register 3 (SCR3)..................................................................57
8.3.8 System Control Register 4 (SCR4).................................................................58
8.3.9 Transmit FIFO Status Register (TFSR)............................................................59
8.3.10 Receive FIFO Status Register (RFSR)............................................................59
8.3.11 Location Control Register (LCR) .....................................................................59
8.3.12 Node Identity Register (BIR)............................................................................60
8.3.13 Net Identity Register (NIR) ..............................................................................60
8.3.14 System Status Register (SSR) ........................................................................61
8.3.15 Packet Size Register (PSR) ............................................................................62
8.3.16 Carrier Sense Register (CSR).........................................................................62
8.4 Interrupt Registers ..........................................................................................63
8.4.1 Interrupt Enable Register (IER) .......................................................................63
8.4.2 Interrupt Identification Register (IIR)................................................................64
8.5 List of BB Register Mapping............................................................................65
8.6 MCU BB Control Registers .............................................................................65
8.6.1 Control Registers List......................................................................................65
8.6.2 BB Control Example........................................................................................66
Direction Serial Peripheral Interface (SPI) ........................................................... 68
9
9.1 Introduction.....................................................................................................68
9.2 Features .........................................................................................................68
9.3 Block Diagram ................................................................................................68
9.4 Transceiver Timing..........................................................................................69
9.5 Related Registers with SPI .............................................................................69
Product Specification (V1.0) 10.09.2007
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ELAN [ ELAN MICROELECTRONICS CORP ]
