Contents
7.1.20 ADC Converting Value – ADDATA...................................................................29
7.1.21 PWM Duty – DT0L/DT0H & DT1L/DT1H.........................................................29
7.1.22 PWM Period – PRD0L/PRD0H & PRD1L/PRD1H...........................................29
7.1.23 PWM Duty Latch – DL0L/DL0H & DL1L/DL1H................................................30
7.1.24 BB Address Register – RFAAR .......................................................................30
7.1.25 BB Data Buffer Register – RFDB.....................................................................30
7.1.26 BB Data Read/Write Control Register – RFACR .............................................30
7.1.27 BB Interrupt Flag Register – RFINTF ..............................................................30
7.2 Dual Port Register ..........................................................................................31
7.3 System Status, Control and Configuration Registers.......................................31
7.3.1 Peripherals Enable Control – PRIE .................................................................31
7.3.2 Interrupts Enable Control – INTE ....................................................................31
7.3.3 Key Wake-up Enable Control – KWUAIE & KWUBIE......................................32
7.3.4 External Interrupts Edge Control – EINTED ....................................................32
7.3.5 Serial Peripheral Serial (SPI) Enable Control Register – SPIC........................33
7.3.6 I/O Control Registers – IOCA~IOCF................................................................33
7.3.7 Pull-up Resistance Control Registers for Ports A~F – PUCA~PUCF...............34
7.3.8 Open Drain Control Registers of Port B/Port C – ODCB/ODCC......................34
7.3.9 Timer Clock Counter Controller – TCCC .........................................................34
7.3.10 Free Run Counter Controller – FRCC .............................................................35
7.3.11 Watchdog Timer Controller – WDTC ...............................................................35
7.3.12 ADC Analog Input Pin Select – ADCAIS.........................................................36
7.3.13 ADC Configuration Register – ADCCR............................................................36
7.3.14 PWM Control Register – PWMCR...................................................................37
7.3.15 BB Interrupt Control Register – RFINTE..........................................................37
7.4 Code Option (ROM-0x2FFF)...........................................................................38
8
Baseband (BB)....................................................................................................... 39
8.1 BB: Standard Interface for the RFW102 Series...............................................39
8.1.1 Features..........................................................................................................39
8.1.2 Description ......................................................................................................39
8.1.3 I/O and Package Description...........................................................................40
8.1.4 BB Architecture ...............................................................................................42
8.2 BB Description................................................................................................42
8.2.1 Reset...............................................................................................................42
8.2.2 Power Saving Modes ......................................................................................42
8.2.2.1 Power-Down Mode...........................................................................42
8.2.2.2 Idle Mode..........................................................................................43
8.2.3 Preamble Correlation ......................................................................................43
8.2.4 Refresh Bit ......................................................................................................44
8.2.5 Bit Structure.....................................................................................................44
8.2.6 CRC ................................................................................................................45
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Product Specification (V1.0) 10.09.2007