EM73PA88A
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
P21 is the control port of watch-dog-timer, and the WDT time up signal is connected to RESET.
Port 21
3
2
1
0
Initial value :0000
CWC
*
*
WDT
CWC
0
1
Clear watchdog timer counter
Clear counter then return to 1
Nothing
WDT
0
1
Set watch-dog-timer detect time
3 x 213/LXIN = 3 x 213/32K Hz = 0.75 sec
7 x 213/LXIN = 7 x 213/32K Hz = 1.75 sec
PROGRAM EXAMPLE
To enable WDT with 7 x 213/LXIN detection time.
LDIA #0001B
OUTA P21; set WDT detection time and clear WDT counter
:
:
RESETTING FUNCTION
When CPU in normal working condition and RESET pin is held in low level for three instruction cycles at least,
then CPU begins to initialize the whole internal states, when RESET pin changes to high level, CPU begins
to work in normal condition.
The CPU internal state during reset condition is as following table :
Hardware condition in RESET state
Program counter
Initial value
0000h
Status flag
01h
Interrupt enable flip-flop ( EI )
MASK0 ,1, 2, 3
00h
00h
Interrupt latch ( IL )
P3, 9, 14, 16, 19, 21, 22, 25, 26, 27, 28, 29, 30
P5
00h
00h
07h
P0, 4, 6, 7, 8, 17, 23, 24
CLK, LXIN
0Fh
Startoscillation
The RESET pin is a hysteresis input pin and it has a pull-up resistor available by mask option.
The simplest RESET circuit is connect RESET pin with a capacitor to VSS and a diode to VDD.
RESET
* This specification are subject to be changed without notice.
10.8.2001
30
ELAN [ ELAN MICROELECTRONICS CORP ]
