EM65570
68COM/ 98SEG 65K Color STN LCD Driver
The CV5~CV0 registers control the Vop calibration offset voltage selection.
VBA = (1+ (M + offset) / 381)* VREF
M: DV register setting
offset: CV5~CV0 setting
CV5~CV0
011111
011110
…
Calibration Offset
+31
+30
…
000001
000000
100000
100001
…
+1
0
-32
-31
…
111111
-1
8.2.28 EEPROM Address Select Register
D7 D6 D5 D4 D3 D2 D1
D0
CSB RS RDB WRB RE2 RE1 RE0
1
0
1
0
*
*
NIB1 NIB0
0
1
1
0
1
0
0
* Don’t Care
(At the time of reset: {NIB1, NIB0} = 0H, read address: AH)
The NIB register selects low nibble or high nibble data to access from EEPROM.
NIB1
NIB0
EEPROM Address
Bank 4[6H] (CV3~CV0)
Bank 4[7H] (CV5~CV4)
0
0
0
1
NOTE
1: When setting CV5~CV0, you must set CV5~CV4 (upper nibble register) first, then set
CV3~CV0 (lower nibble register), and then start to program.
2: The programming sequence of CV5~CV4 and CV3~CV0 is not restricted.
3: When reading from CV5~CV0, you must read EEPROM data to CV5~CV4 (upper
nibble register) first, then read the EEPROM data to CV3~CV0 (lower nibble register).
Product Specification (V1.0) 09.05.2005
(This specification is subject to change without further notice)
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ELAN [ ELAN MICROELECTRONICS CORP ]
