EM65570
68COM/ 98SEG 65K Color STN LCD Driver
After completing the 8-bit data transfer or when making no access, be sure to set the
serial clock input (SCL) to “L”. Care should be taken during board wiring to avoid
external noise from contaminating the SDA and SCL signals. To prevent transfer error
due to external noise, release chip select (CSB = “H”) after every complete 8-bit data
transfer.
CSB
RS
D7
D6
D5
D4
D3
D2
D1
D0
SDA
SCL
1
2
3
4
5
6
7
8
Figure 7-2 4-Wire Type Serial Interface
7.1.5.2 3-Wire Type Serial Interface
When the chip select is active (CSB = “L”), the 3-wire serial interface works through the
SDA and SCL input pins. When chip select is inactive (CSB = “H”), the internal shift
register and counter are reset to the initial condition. Serial data SDA are input
sequentially in the order of RS, D7 to D0 at the rising edge of the serial clock (SCL).
The first serial input data (RS) and the SPOL pin determine whether serial data input
(SDA) is used as display RAM data or as control register data.
SPOL = “0”
Display RAM/Register
Display RAM Data
SPOL = “1”
Display RAM/Register
Control Register Data
Display RAM Data
RS
0
RS
0
1
Control Register Data
1
After completing the 9-bit data transfer or when making no access, be sure to set the
serial clock input (SCL) to “L”. Care should be taken during board wiring to avoid
external noise from contaminating the SDA and SCL signals To prevent transfer error
due to external noise, release chip select (CSB = “H”) after every complete 9-bit data
transfer.
CSB
RS
D7
D6
D5
D4
D3
D2
D1
D0
SDA
SCL
1
2
3
4
5
6
7
8
9
Figure 7-3 3-Wire Type Serial Interface
18 •
Product Specification (V1.0) 09.05.2005
(This specification is subject to change without further notice)
ELAN [ ELAN MICROELECTRONICS CORP ]
