EM65101
128COM/160SEG 16 Gray Scale Level LCD Driver
8.2.25 EEPROM Address Select Register
D7 D6 D5 D4 D3 D2 D1 D0
NIB1 NIB0
CSB RS RDB WRB RE2 RE1 RE0
0
1
0
1
0
1
1
0
0
1
0
*
*
* = Don’t Care
(At the time of reset: {NIB1, NIB0} = 0H, read address: 5H)
The NIB register selects whether to access the low nibble or high nibble data of
EEPROM.
NIB1
NIB0
EEPROM Address
0
0
0
1
Bank 2[1H] (CV3~CV0)
Bank 2[2H] (CV5~CV4)
NOTE
ꢀ
When settings CV5~CV0, you must set CV5~CV4 (upper nibble registers) first,
then set CV3~CV0 (lower nibble registers), and then start program execution.
ꢀ
ꢀ
The programming sequence of CV5~CV4 and CV3~CV0 has no restriction.
When reading from CV5~CV0, you must read EEPROM data to CV5~CV4
(upper nibble registers) first, then read EEPROM data to CV3~CV 0(lower
nibble registers).
8.2.26 Scroll Top Address
D7 D6 D5 D4 D3 D2 D1 D0
CSB RS RDB WRB RE2 RE1 RE0
STA3 STA2 STA1 STA0
0
1
1
0
0
1
1
0
0
1
0
(At the time of reset: {STA3, STA2, STA1, STA0} = 0H, read address: 6H)
D7 D6 D5 D4 D3 D2 D1 D0
CSB RS RDB WRB RE2 RE1 RE0
STA6 STA5 STA4
0
1
1
1
0
1
1
0
0
1
0
*
* = Don’t Care
(At the time of reset: {STA6, STA5, STA4} = 0H, read address: 7H)
Set the top address of scroll data area in RAM. 0 <= Scroll top address <= 127; Scroll
top address must be less than the Scroll bottom address
STA6
STA5
STA4
STA3
STA2
STA1
STA0
Top Common Line
0
0
:
0
0
:
0
0
:
0
0
:
0
0
:
0
0
:
0
1
:
COM0
COM1
:
1
:
1
:
0
:
0
:
0
:
1
:
1
:
COM99
:
1
1
1
1
1
1
1
COM127
Product Specification (V0.4) 08.15.2005
• 61
(This specification is subject to change without further notice)
ELAN [ ELAN MICROELECTRONICS CORP ]
