EM65101
128COM/160SEG 16 Gray Scale Level LCD Driver
8.2 Functions of the Control Registers
The EM65101 has many control registers. When accessing the control registers, the
upper nibble of the data bus (D7~D4) represent the register address while the lower
nibble of the data bus (D3~D0) represent data. The following figure shows an access
example. The Pins CSB, RS, RDB, & WRB) settings are for the 80-family MPU
interface. Only the setting of the terminals RDB & WRB are different when it is
accessed by the 68-family MPU.
(Example) X Address:
D7
D6
D5
D4
D3
D2
D1
D0
CSB
0
RS
1
RDB WRB RE2 RE1 RE0
0
0
0
0
AX3 AX2 AX1 AX0
1
0
0
0
0
Register address
Data
Pins setting
Register Bank
When writing to the control register, it is used directly by addressing D7~D4 of the data
bus. When reading, you must first set the RA register for the specific register address
before you can read specific register. Therefore, a 2-step procedure is required to
perform a read register operation. After reading, the specific register will output to
D3~D0 of the data bus. All nibbles, except D3~D0, of the data bus are all “H.” Access
to undefined register address area is prohibited. When RS is “L,” all read/write
operations are accessed to display RAM. Then the data bus does not include the
register address. When writing, D3~D0 data is written to the register designated at
D7~D4 on the rising edge of the WRB signal. When reading, the register can output to
data bus during RDB active period. The control register and display RAM have equal
access sequence
8.2.1 X Address Register (AX)
D7 D6 D5 D4 D3 D2 D1 D0
AY3 AX2 AY1 AY0
CSB RS RDB WRB RE2 RE1 RE0
0
0
0
0
0
1
1
0
0
0
0
(At the time of reset: {AX3, AX2, AX1, AX0} = 0H, read address: 0H)
D7 D6 D5 D4 D3 D2 D1 D0
AX7 AX6 AX5 AX4
CSB RS RDB WRB RE2 RE1 RE0
0
0
0
1
0
1
1
0
0
0
0
(At the time of reset: {AX7, AX6, AX5, AX4} = 0H, read address: 1H)
The AX register is set to X-direction address of display RAM. In data setting, command
is divided into lower and upper sections at 4-bit of data each in order to accommodate
the required 8-bit of total data.
8.2.2 Y Address Register (AY)
D7 D6 D5 D4 D3 D2 D1 D0
AY3 AX2 AY1 AY0
CSB RS RDB WRB RE2 RE1 RE0
0
0
1
0
0
1
1
0
0
0
0
(At the time of reset: {AY3, AY2, AY1, AY0} =0H, read address: 2H)
The AY register is set to Y-direction address of display RAM. 00H to 0FH are
applicable to the values for AY3 to AY0.
44 •
Product Specification (V0.4) 08.15.2005
(This specification is subject to change without further notice)
ELAN [ ELAN MICROELECTRONICS CORP ]
