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HM5225805BLTT-75 参数 Datasheet PDF下载

HM5225805BLTT-75图片预览
型号: HM5225805BLTT-75
PDF下载: 下载PDF文件 查看货源
内容描述: LVTTL 256M SDRAM接口的133 MHz / 100 MHz的4 Mword 】 16位】 4银行/ 8 - Mword 】 8位】 4银行/ 16 Mword 】 4位】 4银行PC / 133 , PC / 100 SDRAM [256M LVTTL interface SDRAM 133 MHz/100 MHz 4-Mword 】 16-bit 】 4-bank/8-Mword 】 8-bit 】 4-bank /16-Mword 】 4-bit 】 4-bank PC/133, PC/100 SDRAM]
分类和应用: 存储内存集成电路光电二极管动态存储器PC时钟
文件页数/大小: 63 页 / 454 K
品牌: ELPIDA [ ELPIDA MEMORY ]
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HM5225165B-75/A6/B6  
HM5225805B-75/A6/B6  
HM5225405B-75/A6/B6  
256M LVTTL interface SDRAM  
133 MHz/100 MHz  
4-Mword × 16-bit × 4-bank/8-Mword × 8-bit × 4-bank  
/16-Mword × 4-bit × 4-bank  
PC/133, PC/100 SDRAM  
E0082H10 (1st edition)  
(Previous ADE-203-1073B (Z))  
Jan. 31, 2001  
Description  
The HM5225165B is a 256-Mbit SDRAM organized as 4194304-word × 16-bit × 4 bank. The HM5225805B  
is a 256-Mbit SDRAM organized as 8388608-word × 8-bit × 4 bank. The HM5225405B is a 256-Mbit  
SDRAM organized as 16777216-word × 4-bit × 4 bank. All inputs and outputs are referred to the rising edge  
of the clock input. It is packaged in standard 54-pin plastic TSOP II.  
Features  
3.3 V power supply  
Clock frequency: 133 MHz/100 MHz (max)  
LVTTL interface  
Single pulsed RAS  
4 banks can operate simultaneously and independently  
Burst read/write operation and burst read/single write operation capability  
Programmable burst length: 1/2/4/8  
2 variations of burst sequence  
Sequential (BL = 1/2/4/8)  
Interleave (BL = 1/2/4/8)  
Programmable CAS latency: 2/3  
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.