HM51W16165 Series, HM51W18165 Series
Truth Table
RAS
LCAS
UCAS
WE
D
OE
Output
Open
Valid
Operation
Standby
H
D
L
D
H
L
D
L
H
L
Lower byte Read cycle
Upper byte
L
H
L
H
L
Valid
L
L
H
L
Valid
Word
L
L
H
L
L*2
L*2
L*2
L*2
L*2
L*2
H to L
H to L
H to L
D
D
Open
Open
Open
Lower byte Early write cycle
Upper byte
L
H
L
D
L
L
D
Word
L
L
H
L
H
Undefined Lower byte Delayed write cycle
Undefined Upper byte
L
H
L
H
L
L
H
Undefined Word
L
L
H
L
L to H
L to H
L to H
D
Valid
Valid
Valid
Open
Open
Open
Open
Open
Lower byte Read-modify-write cycle
L
H
L
Upper byte
Word
L
L
L
H
H
L
H
L
Word
Word
Word
Word
RAS-only refresh cycle
H to L
H to L
H to L
L
D
D
CAS-before-RAS refresh cycle or
Self refresh cycle (L-version)
H
L
D
D
L
D
D
L
L
H
H
Read cycle (Output disabled)
Notes: 1. H: High (inactive) L: Low (active) D: H or L
2. tWCS ≥ 0 ns Early write cycle
tWCS < 0 ns Delayed write cycle
3. Mode is determined by the OR function of the UCAS and LCAS. (Mode is set by the earliest of
UCAS and LCAS active edge and reset by the latest of UCAS and LCAS inactive edge.)
However write OPERATION and output HIZ control are done independently by each UCAS,
LCAS.
ex. if RAS = H to L, UCAS = H, LCAS = L, then CAS-before-RAS refresh cycle is selected.
Data Sheet E0153H10
6
ELPIDA [ ELPIDA MEMORY ]
