EDS2532CABJ
Mode Register Configuration
The mode register is set by the input to the address pins (A0 to A11, BA0 and BA1) during mode register set cycles.
The mode register consists of five sections, each of which is assigned to address pins.
BA1, BA0, A8, A9, A10, A11: (OPCODE): The SDRAM has two types of write modes. One is the burst write mode,
and the other is the single write mode. These bits specify write mode.
Burst read and burst write: Burst write is performed for the specified burst length starting from the column address
specified in the write cycle.
Burst read and single write: Data is only written to the column address specified during the write cycle, regardless of
the burst length.
A7: Keep this bit Low at the mode register set cycle. If this pin is high, the vender test mode is set.
A6, A5, A4: (LMODE): These pins specify the /CAS latency.
A3: (BT): A burst type is specified.
A2, A1, A0: (BL): These pins specify the burst length.
A11
OPCODE
BA1 BA0
A10
A9
A8
A7
0
A6
A5
A4
A3
BT
A2
A1
BL
A0
LMODE
A6 A5 A4 CAS latency
A3 Burst type
Burst length
BT=0 BT=1
A2 A1 A0
R
R
2
0
0
0
0
1
0
0
1
1
X
0
1
0
1
X
0
1
Sequential
Interleave
1
2
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
2
3
4
4
R
8
8
R
R
R
R
R
R
A9 A8
Write mode
A10
BA1
0
BA0
0
A11
R
0
X
X
X
X
X
X
0
0
0
Burst read and burst write
F.P.
0
1
X
X
X
X
X
X
0
0
0
0
1
1
0
0
0
1
0
1
R
1
0
R
1
1
R
R
X
X
F.P.: Full Page
R is Reserved (inhibit)
X: 0 or 1
Burst read and single write
R
X
X
X
X
Mode Register Set Timing
Data Sheet E0460E40 (Ver. 4.0)
20
ELPIDA [ ELPIDA MEMORY ]
