EDS2504ACTA/08ACTA/16ACTA, EDS2504APTA/08APTA/16APTA
Bank active command interval
1. Same bank: The interval between the two bank active commands must be no less than tRC.
2. In the case of different bank active commands: The interval between the two bank active commands must be no
less than tRRD.
CLK
Command
Address
BS
ACT
ACT
ROW
ROW
tRC
Bank 0
Active
Bank 0
Active
Bank Active to Bank Active for Same Bank
CLK
Command
Address
ACT
ACT
ROW:0
ROW:1
BS
tRRD
Bank 0
Active
Bank 3
Active
Bank Active to Bank Active for Different Bank
Mode register set to Bank active command interval
The interval between setting the mode register and executing a bank active command must be no less than lMRD.
CLK
Command
Address
MRS
ACT
OPCODE
BS & ROW
IMRD
Mode
Register Set
Bank
Active
Mode register set to Bank active command interval
Data Sheet E0110E30 (Ver. 3.0)
39
ELPIDA [ ELPIDA MEMORY ]
