欢迎访问ic37.com |
会员登录 免费注册
发布采购

EDS2516APTA-7AL 参数 Datasheet PDF下载

EDS2516APTA-7AL图片预览
型号: EDS2516APTA-7AL
PDF下载: 下载PDF文件 查看货源
内容描述: 256M位的SDRAM [256M bits SDRAM]
分类和应用: 动态存储器
文件页数/大小: 51 页 / 553 K
品牌: ELPIDA [ ELPIDA MEMORY ]
 浏览型号EDS2516APTA-7AL的Datasheet PDF文件第21页浏览型号EDS2516APTA-7AL的Datasheet PDF文件第22页浏览型号EDS2516APTA-7AL的Datasheet PDF文件第23页浏览型号EDS2516APTA-7AL的Datasheet PDF文件第24页浏览型号EDS2516APTA-7AL的Datasheet PDF文件第26页浏览型号EDS2516APTA-7AL的Datasheet PDF文件第27页浏览型号EDS2516APTA-7AL的Datasheet PDF文件第28页浏览型号EDS2516APTA-7AL的Datasheet PDF文件第29页  
EDS2504ACTA/08ACTA/16ACTA, EDS2504APTA/08APTA/16APTA  
Burst length = 2  
Burst length = 4  
Starting Ad. Addressing(decimal)  
Starting Ad. Addressing(decimal)  
A0  
0
Sequential Interleave  
A1  
0
A0 Sequential  
Interleave  
0, 1,  
1, 0,  
0, 1,  
1, 0,  
0
1
0
1
0, 1, 2, 3,  
1, 2, 3, 0,  
2, 3, 0, 1,  
0, 1, 2, 3,  
1, 0, 3, 2,  
2, 3, 0, 1,  
3, 2, 1, 0,  
1
0
1
1
3,  
0, 1, 2,  
Burst length = 8  
Starting Ad.  
Addressing(decimal)  
A2 A1 A0 Sequential  
Interleave  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0, 1, 2, 3, 4, 5, 6, 7,  
1, 2, 3, 4, 5, 6, 7, 0,  
2, 3, 4, 5, 6, 7, 0, 1,  
3, 4, 5, 6, 7, 0, 1, 2,  
4, 5, 6, 7, 0, 1, 2, 3,  
5, 6, 7, 0, 1, 2, 3, 4,  
6, 7, 0, 1, 2, 3, 4, 5,  
7, 0, 1, 2, 3, 4, 5, 6,  
0, 1, 2, 3, 4, 5, 6, 7,  
1, 0, 3, 2, 5, 4, 7, 6,  
2, 3, 0, 1, 6, 7, 4, 5,  
3, 2, 1, 0, 7, 6, 5, 4,  
4, 5, 6, 7, 0, 1, 2, 3,  
5, 4, 7, 6, 1, 0, 3, 2,  
6, 7, 4, 5, 2, 3, 0, 1,  
7, 6, 5, 4, 3, 2, 1, 0,  
Burst Sequence  
Power-up sequence  
Power-up sequence  
The SDRAM should be goes on the following sequence with power up.  
The CLK, CKE, /CS, DQM and DQ pins keep low till power stabilizes.  
The CLK pin is stabilized within 100 µs after power stabilizes before the following initialization sequence.  
The CKE and DQM is driven to high between power stabilizes and the initialization sequence.  
This SDRAM has VDD clamp diodes for CLK, CKE, /CS DQM and DQ pins. If these pins go high before power up,  
the large current flows from these pins to VDD through the diodes.  
Initialization sequence  
When 200 µs or more has past after the above power-up sequence, all banks must be precharged using the  
precharge command (PALL). After tRP delay, set 8 or more auto refresh commands (REF). Set the mode register  
set command (MRS) to initialize the mode register. We recommend that by keeping DQM and CKE to High, the  
output buffer becomes High-Z during Initialization sequence, to avoid DQ bus contention on memory system formed  
with a number of device.  
Initialization sequence  
Power up sequence  
100 µs  
200 µs  
VDD, VDDQ 0 V  
Low  
Low  
Low  
CKE, DQM  
CLK  
/CS, DQ  
Power stabilize  
Power-up sequence and Initialization sequence  
Data Sheet E0110E30 (Ver. 3.0)  
25  
 复制成功!