EDS2504ACTA/08ACTA/16ACTA, EDS2504APTA/08APTA/16APTA
Operation of the SDRAM
Read/Write Operations
Bank active
Before executing a read or write operation, the corresponding bank and the row address must be activated by the
bank active (ACT) command. An interval of tRCD is required between the bank active command input and the
following read/write command input.
Read operation
A read operation starts when a read command is input. Output buffer becomes Low-Z in the (/CAS Latency - 1)
cycle after read command set. The SDRAM can perform a burst read operation.
The burst length can be set to 1, 2, 4 and 8. The start address for a burst read is specified by the column address
and the bank select address at the read command set cycle. In a read operation, data output starts after the number
of clocks specified by the /CAS Latency. The /CAS Latency can be set to 2 or 3.
When the burst length is 1, 2, 4 and 8 the DOUT buffer automatically becomes High-Z at the next clock after the
successive burst-length data has been output.
The /CAS latency and burst length must be specified at the mode register.
CLK
tRCD
Command
Address
READ
ACT
Row
Column
out 3
out 1 out 2
out 0
out 1 out 2
CL = 2
CL = 3
DQ
out 3
out 0
CL = /CAS latency
Burst Length = 4
/CAS Latency
CLK
Command
Address
tRCD
ACT
Row
READ
Column
out 0
BL = 1
out 0 out 1
BL = 2
BL = 4
BL = 8
DQ
out 3
out 0 out 1 out 2
out 0 out 1 out 2
out 3
out 5 out 6 out 7
out 4
BL : Burst Length
/CAS Latency = 2
Burst Length
Data Sheet E0110E30 (Ver. 3.0)
26
ELPIDA [ ELPIDA MEMORY ]
