EDS2504ACTA/08ACTA/16ACTA, EDS2504APTA/08APTA/16APTA
Current state
/CS
H
L
/RAS /CAS /WE
Address
Command
DESL
Operation
NOP
Mode register set
×
×
×
×
H
H
H
H
L
H
H
L
H
L
×
NOP
NOP
L
×
BST
ILLEGAL
L
H
L
BA, CA, A10
BA, CA, A10
BA, RA
BA, A10
×
READ/READA
WRIT/WRITA
ACT
ILLEGAL*4
ILLEGAL*4
Bank and row active*9
NOP
Refresh*9
Mode register set*8
L
L
L
H
H
L
H
L
L
L
PRE, PALL
REF, SELF
MRS
L
L
H
L
L
L
L
MODE
Remark: H: VIH. L: VIL. ×: VIH or VIL
Notes: 1.An interval of tDPL is required between the final valid data input and the precharge command.
2. If tRRD is not satisfied, this operation is illegal.
3. Illegal for same bank, except for another bank.
4. Illegal for all banks.
5. NOP for same bank, except for another bank.
6. Illegal if tRCD is not satisfied.
7. Illegal if tRAS is not satisfied.
8. MRS command must be issued after DOUT finished, in case of DOUT remaining.
9. Illegal if lMRD is not satisfied.
Data Sheet E0110E30 (Ver. 3.0)
20
ELPIDA [ ELPIDA MEMORY ]
