EDS2504ACTA/08ACTA/16ACTA, EDS2504APTA/08APTA/16APTA
Function Truth Table
The following table shows the operations that are performed when each command is issued in each mode of the
SDRAM.
The following table assumes that CKE is high.
Current state
/CS
/RAS /CAS /WE
Address
Command
Operation
Precharge
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
L
L
L
L
×
×
×
×
DESL
Enter IDLE after tRP
Enter IDLE after tRP
ILLEGAL
ILLEGAL*3
ILLEGAL*3
ILLEGAL*3
NOP*5
H
H
H
H
L
H
H
L
H
L
×
NOP
×
BST
H
L
BA, CA, A10
READ/READA
WRIT/WRITA
ACT
L
BA, CA, A10
H
H
L
H
L
BA, RA
L
BA, A10
PRE, PALL
REF, SELF
MRS
L
H
L
×
ILLEGAL
L
L
MODE
ILLEGAL
Idle
×
×
×
×
DESL
NOP
H
H
H
H
L
H
H
L
H
L
×
NOP
NOP
×
BST
ILLEGAL
H
L
BA, CA, A10
READ/READA
WRIT/WRITA
ACT
ILLEGAL*4
ILLEGAL*4
Bank and row active
NOP
L
BA, CA, A10
H
H
L
H
L
BA, RA
L
BA, A10
PRE, PALL
REF, SELF
MRS
L
H
L
×
Refresh
Mode register set*8
L
L
MODE
Row active
×
×
×
×
DESL
NOP
H
H
H
H
H
H
L
H
L
×
NOP
NOP
×
BST
ILLEGAL
H
L
BA, CA, A10
BA, CA, A10
READ/READA
WRIT/WRITA
Begin read*6
Begin write*6
L
Other bank active
L
L
H
H
BA, RA
ACT
ILLEGAL on same bank*2
L
L
L
H
L
L
L
H
L
L
BA, A10
PRE, PALL
REF, SELF
MRS
Precharge*7
L
H
L
×
ILLEGAL
L
L
MODE
ILLEGAL
Read
×
H
H
×
×
H
L
×
×
×
DESL
Continue burst to end
Continue burst to end
Burst stop
H
H
NOP
BST
Continue burst read to /CAS
latency and New read
L
L
L
H
H
L
L
L
H
L
BA, CA, A10
BA, CA, A10
BA, RA
READ/READA
WRIT/WRITA
ACT
Term burst read/start write
Other bank active
H
H
ILLEGAL on same bank*2
L
L
L
L
L
L
H
L
L
L
H
L
BA, A10
×
PRE, PALL
REF, SELF
MRS
Term burst read and Precharge
ILLEGAL
MODE
ILLEGAL
Data Sheet E0110E30 (Ver. 3.0)
18
ELPIDA [ ELPIDA MEMORY ]
