EDJ1108BABG, EDJ1116BABG
Read Operation
During read or write command DDR3 will support BC4 and BL8 on the fly using address A12 during the READ or
WRITE (auto precharge can be enabled or disabled).
• A12 = 0, BC4 (BC4 = burst chop, tCCD = 4)
• A12 = 1, BL8
A12 will be used only for burst length control, not a column address.
The Burst Read command is initiated by having /CS and /CAS low while holding /RAS and /WE high at the rising
edge of the clock. The address inputs determine the starting column address for the burst. The delay from the start
of the command to when the data from the first cell appears on the outputs is equal to the value of the read latency
(RL). The data strobe output (DQS) is driven low 1 clock cycle before valid data (DQ) is driven onto the data bus.
The first bit of the burst is synchronized with the rising edge of the data strobe (DQS). Each subsequent data-out
appears on the DQ pin in phase with the DQS signal in a source synchronous manner.
The RL is equal to an additive latency (AL) plus /CAS latency (CL). The CL is defined by the mode register 0 (MR0),
similar to the existing SDR and DDR-I SDRAMs. The AL is defined by the mode register 1
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
CK
/CK
Command*3
Address*4
READ
NOP
Bank
Col n
tRPST
tRPRE
DQS, /DQS
DQ*2
Dout Dout Dout
n+1 n+2 n+3
Dout Dout Dout
n+5 n+6 n+7
Dout
n
Dout
n+4
CL = 5
RL = AL + CL
VIH or VIL
Notes: 1. BL8, AL = 0, RL = 5, CL = 5
2. Dout n = data-out from column n.
3. NOP commands are shown for ease of illustration; other commands may be valid at these times.
4. BL8 setting activated by MR0 bit [A1, A0] = [0, 0] or MR0 bit [A1, A0] = [0, 1] and A12 = 1 during READ command at T0.
Burst Read Operation, RL = 5
Data Sheet E1248E40 (Ver. 4.0)
102
ELPIDA [ ELPIDA MEMORY ]
