EDJ1108BABG, EDJ1116BABG
Multi Purpose Register (MR3)
The Multi Purpose Register (MPR) function is used to read out predefined system timing calibration bit sequence.
Conceptual Block Diagram of Multi Purpose Register
To enable the MPR, a mode register set (MRS) command must be issued to MR3 register with bit A2 = 1. Prior to
issuing the MRS command, all banks must be in the idle state (all banks precharged and tRP/tRPA met). Once the
MPR is enabled, any subsequent READ or READA commands will be redirected to the multi purpose register. The
resulting operation when a READ or READA command is issued is defined by MR3 bits [A1: A0] when the MPR is
enabled. When the MPR is enabled, only READ or READA commands are allowed until a subsequent MRS
command is issued with the MPR disabled (MR3 bit A2=0). Power-down mode, self-refresh, and any other non-
READ/READA command are not allowed during MPR enable mode. The /RESET function is supported during MPR
enable mode.
[Functional Description of MR3 Bits for MPR]
MR3
A2
A [1:0]
MPR
MPR-Loc
Function
Notes
1
Normal operation, no MPR transaction.
All subsequent reads will come from DRAM array.
All subsequent WRITEs will go to DRAM array.
Enable MPR mode, subsequent READ/READA commands defined by MR3 A [1:0]
bits.
Don’t care
(0 or 1)
0
1
MR3 A [1:0]
Note: 1. See Available Data Locations and Burst Order Bit Mapping for Multi Purpose Register table
Data Sheet E1248E40 (Ver. 4.0)
90
ELPIDA [ ELPIDA MEMORY ]
