EDJ1108BABG, EDJ1116BABG
Command Operation
Command Truth Table
The DDR3 SDRAM recognizes the following commands specified by the /CS, /RAS, /CAS, /WE and address pins.
CKE
Previous Current
BA0 to A12
A10
(AP)
Address
Function
Symbol cycle
cycle
/CS /RAS /CAS /WE BA2
(/BC)
Notes
Mode register set
Auto-refresh
MRS
REF
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
BA
V
op-code
H
H
V
V
V
V
V
V
Self-refresh entry
SELF
V
6, 8, 11
6, 7, 8,
11
Self-refresh exit
SREX
L
H
H
×
×
×
×
×
×
×
L
H
H
H
H
H
H
H
L
L
L
L
L
L
L
H
L
H
H
H
H
L
H
L
L
H
L
L
L
V
V
V
L
V
V
V
Single bank precharge
Precharge all banks
Bank activate
PRE
H
H
H
H
H
H
BA
V
V
PALL
ACT
L
V
H
L
BA
BA
BA
BA
RA
V
12
Write (Fixed BL)
WRIT
WRS4
WRS8
H
H
H
L
L
L
CA
CA
CA
Write (BC4, on the fly)
L
L
Write (BL8, on the fly)
L
H
Write with auto precharge
(Fixed BL)
Write with auto precharge
(BC4, on the fly)
Write with auto precharge
(BL8, on the fly)
WRITA
WRAS4
WRAS8
H
H
H
H
H
H
L
L
L
H
H
H
L
L
L
L
L
L
BA
BA
BA
V
L
H
H
H
CA
CA
CA
H
Read (Fixed BL)
READ
RDS4
RDS8
H
H
H
H
H
H
L
L
L
H
H
H
L
L
L
H
H
H
BA
BA
BA
V
L
L
L
L
CA
CA
CA
Read (BC4, on the fly)
Read (BL8, on the fly)
H
Read with auto precharge
READA
RDAS4
RDAS8
H
H
H
H
H
H
L
L
L
H
H
H
L
L
L
H
H
H
BA
BA
BA
V
L
H
H
H
CA
CA
CA
(Fixed BL)
Read with auto precharge
(BC4, on the fly)
Read with auto precharge
(BL8, on the fly)
H
No operation
NOP
H
H
H
H
L
H
H
L
L
H
H
L
H
×
H
×
H
×
V
×
×
V
×
V
×
×
V
×
×
V
×
V
×
×
V
×
V
×
×
V
×
V
×
×
9
Device deselect
DESL
PDEN
10
Power-down mode entry
×
×
×
×
5, 11
L
H
×
H
×
H
×
V
×
Power-down mode exit
PDEX
H
H
H
H
H
L
5, 11
L
H
H
H
H
H
H
H
L
V
H
L
ZQ calibration long
ZQ calibration short
ZQCL
ZQCS
H
H
L
L
L
Remark: H = VIH. L = VIL. × = Don't care (defined or undefined (including floating around VREF)) logic level.
V = VIH or VIL (defined logic level).
BA = Bank addresses. RA = Row Address. CA = Column Address. /BC = Burst Chop.
Data Sheet E1248E40 (Ver. 4.0)
66
ELPIDA [ ELPIDA MEMORY ]
