EDJ1108BABG, EDJ1116BABG
Pin Configurations (×8 configuration)
/xxx indicates active low signal.
78-ball FBGA (×8 configuration)
1
2
3
7
8
9
A
B
VSS
VDD
NC
NU/(/TDQS) VSS
VDD
VSS VSSQ DQ0
VDDQ
DM/TDQS VSSQ VDDQ
C
D
DQ2 DQS
DQ1
VDD
DQ7
DQ3 VSSQ
VSSQ
VSSQ DQ6 /DQS
VSS
DQ5
E
F
G
H
J
DQ4
VREFDQ VDDQ
VDDQ
NC
NC
VSS /RAS
CK
/CK
VSS
ODT VDD /CAS
VDD CKE
A10(AP)
NC
/CS
/WE
ZQ
NC
VSS
VDD
VSS
VDD
VSS
BA0
A3
BA2
A0
NC VREFCA VSS
K
L
A12(/BC) BA1
VDD
VSS
VDD
VSS
A5
A2
A1
A11
NC
A4
A6
A8
M
N
A7
A9
/RESET A13
(Top view)
Pin name
Function
Address inputs
A10 (AP): Auto precharge
A12(/BC): Burst chop
Pin name
/RESET*3
Function
A0 to A13*3
Active low asynchronous reset
BA0 to BA2*3
DQ0 to DQ7
DQS, /DQS
TDQS, /TDQS
/CS*3
/RAS, /CAS, /WE*3
CKE*3
Bank select
VDD
Supply voltage for internal circuit
Ground for internal circuit
Supply voltage for DQ circuit
Ground for DQ circuit
Reference voltage for DQ
Reference voltage
Data input/output
Differential data strobe
Termination data strobe
Chip select
VSS
VDDQ
VSSQ
VREFDQ
VREFCA
ZQ
NC*1
NU*2
Command input
Clock enable
Reference pin for ZQ calibration
No connection
CK, /CK
Differential clock input
Write data mask
ODT control
DM
ODT*3
Not usable
Notes: 1. Not internally connected with die.
2. Don’t connect. Internally connected.
3. Input only pins (address, command, CKE, ODT and /RESET) do not supply termination.
Data Sheet E1248E40 (Ver. 4.0)
3
ELPIDA [ ELPIDA MEMORY ]
