EDJ1108BABG, EDJ1116BABG
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11 T12
T13
CK
/CK
Command*3
Address*4
NOP
WRIT
Bank
Col n
tWPST
tWPRE
DQS, /DQS
DQ*2
Din Din Din Din Din Din Din Din
n+1 n+2 n+3 n+4 n+5 n+6 n+7
n
AL = 4
CWL = 5
WL = AL + CWL
VIH or VIL
Notes: 1. BL8, WL = 9 (AL = (CL − 1), CL = 5, CWL = 5)
2. Din n = data-in from column n.
3. NOP commands are shown for ease of illustration; other commands may be valid at these times.
4. BL8 setting activated by MR0 bit [A1, A0] = [0, 0] or MR0 bit [A1, A0] = [0, 1] and A12 = 1 during WRITcommand at T0.
Burst Write Operation, WL = 9
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
Tn Tn+1 Tn+2
CK
/CK
Command*3
Address*4
NOP
WRIT
READ
tWTR*5
Bank
Col n
Bank
Col b
tWPRE
tWPST
DQS, /DQS
DQ*2
Din
n
Din Din Din
n+1 n+2 n+3
WL = 5
RL = 5
Notes: 1. BC4, WL = 5, RL = 5.
2. Din n = data-in from column n; Dout b = data-out from column b.
VIH or VIL
3. NOP commands are shown for ease of illustration; other commands may be valid at these times.
4. BC4 setting activated by MR0 bit [A1, A0] = [1, 0] during WRIT command at T0 and READ command at Tn.
5. tWTR controls the write to read delay to the same device and starts with the first rising clock edge after the
last write data shown at T7.
Write to Read Operation
Data Sheet E1248E40 (Ver. 4.0)
111
ELPIDA [ ELPIDA MEMORY ]
