EDJ1104BBSE, EDJ1108BBSE, EDJ1116BBSE
Register Address Table
The table below provides an overview of the available data locations, how they are addressed by MR3 A [1:0] during
a MR0 to MR3, and how their individual bits are mapped into the burst order bits during a multi purpose register
read.
[Available Data Locations and Burst Order Bit Mapping for Multi Purpose Register]
Read
MR3
A [2]
MR3
A [1:0]
Burst
Length
Function
Address Burst Order and Data Pattern
A [2:0]
Notes
Burst order 0,1,2,3,4,5,6,7
BL8
BC4
BC4
000
1
1
1
Read
Pre-defined pattern [0,1,0,1,0,1,0,1]
predefined
pattern for
system
Burst order 0,1,2,3,
Pre-defined pattern [0,1,0,1]
Burst order 4,5,6,7
Pre-defined pattern [0,1,0,1]
1
00
000
calibration
100
BL8
BC4
BC4
BL8
BC4
BC4
BL8
BC4
BC4
000
000
100
000
000
100
000
000
100
Burst order 0,1,2,3,4,5,6,7
1
1
1
1
1
1
1
1
1
1
1
1
01
10
11
RFU
RFU
RFU
Burst order 0,1,2,3
Burst order 4,5,6,7
Burst order 0,1,2,3,4,5,6,7
Burst order 0,1,2,3
Burst order 4,5,6,7
Burst order 0,1,2,3,4,5,6,7
Burst order 0,1,2,3,
Burst order 4,5,6,7
Note: 1. Burst order bit 0 is assigned to LSB and burst order bit 7 is assigned to MSB of the selected MPR agent.
Relevant Timing Parameters
The following AC timing parameters are important for operating the Multi Purpose Register: tRP, tMRD, tMOD and
tMPRR.
Besides these timings, all other timing parameters needed for proper operation of the DDR3 SDRAM need to be
observed.
[MPR Recovery Time tMPRR]
Symbol
tMPRR
Description
Multi Purpose Register Recovery Time, defined between end of MPR read burst and MRS which
reloads MPR or disables MPR function
Data Sheet E1375E50 (Ver. 5.0)
97
ELPIDA [ ELPIDA MEMORY ]
