EDJ1104BBSE, EDJ1108BBSE, EDJ1116BBSE
Clock Jitter [DDR3-1600, 1333]
-GL, -GN
1600
-DG, -DJ
1333
Data rate (Mbps)
Parameter
Symbol
min.
max.
3333
min.
max.
3333
Unit
ps
Notes
1
Average clock period
tCK (avg)
1250
1500
tCK(avg)min tCK(avg)max tCK(avg)min tCK(avg)max
Absolute clock period
Clock period jitter
Clock period jitter during
DLL locking period
Cycle to cycle period Jitter
Cycle to cycle clock period jitter
during DLL locking period
tCK (abs)
tJIT (per)
+
+
+
+
ps
2
tJIT(per)min tJIT(per)max tJIT(per)min tJIT(per)max
−70
70
−80
80
ps
ps
ps
ps
6
6
7
7
tJIT (per, lck) −60
tJIT (cc)
60
−70
70
140
120
160
140
tJIT (cc, lck)
Cumulative error across 2
cycles
Cumulative error across 3
cycles
Cumulative error across 4
cycles
Cumulative error across 5
cycles
Cumulative error across 6
cycles
Cumulative error across 7
cycles
Cumulative error across 8
cycles
Cumulative error across 9
cycles
Cumulative error across 10
cycles
Cumulative error across 11
cycles
Cumulative error across 12
cycles
Cumulative error across
n = 13, 14…49, 50 cycles
tERR (2per) −103
tERR (3per) −122
tERR (4per) −136
tERR (5per) −147
tERR (6per) −155
tERR (7per) −163
tERR (8per) −169
tERR (9per) −175
tERR (10per) −180
tERR (11per) −184
tERR (12per) −188
103
122
136
147
155
163
169
175
180
184
188
−118
−140
−155
−168
−177
−186
−193
−200
−205
−210
−215
118
140
155
168
177
186
193
200
205
210
215
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
8
8
8
8
8
8
8
8
8
8
8
tERR (nper) min. = (1+0.68in(n)) x tJIT(per) min
tERR (nper) max. = (1+0.68in(n)) x tJIT(per) max
tERR (nper)
tCH (avg)
tCL (avg)
9
tCK
(avg)
tCK
(avg)
tCK
(avg)
tCK
(avg)
Average high pulse width
Average low pulse width
0.47
0.47
0.43
0.43
0.53
0.47
0.47
0.43
0.43
0.53
3
0.53
0.53
4
Absolute clock high pulse width tCH (abs)
Absolute clock low pulse width tCL (abs)
10, 11
10, 12
5
Duty cycle jitter
tJIT (duty)
ps
Data Sheet E1375E50 (Ver. 5.0)
63
ELPIDA [ ELPIDA MEMORY ]
