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EDJ1116BBSE-8A-F 参数 Datasheet PDF下载

EDJ1116BBSE-8A-F图片预览
型号: EDJ1116BBSE-8A-F
PDF下载: 下载PDF文件 查看货源
内容描述: 1G位DDR3 SDRAM [1G bits DDR3 SDRAM]
分类和应用: 存储内存集成电路动态存储器双倍数据速率
文件页数/大小: 151 页 / 1895 K
品牌: ELPIDA [ ELPIDA MEMORY ]
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EDJ1104BBSE, EDJ1108BBSE, EDJ1116BBSE  
[Single-ended levels for CK, DQS, DQSL, DQSU, /CK, /DQS, /DQSL or /DQSU]  
Parameter  
Symbol min.  
typ.  
max.  
Unit  
V
Notes  
1, 2  
3
Single-ended high level for strobes  
Single-ended high level for CK, /CK  
Single-ended low level for strobes  
Single-ended low level for CK, /CK  
(VDD/2) + 0.175  
*
VSEH  
VSEL  
3
(VDD/2) + 0.175  
*
V
1, 2  
3
*
(VDD/2) 0.175 V  
(VDD/2) 0.175 V  
1, 2  
3
*
1, 2  
Notes: 1. For CK, /CK use VIH/VIL(AC) of ADD/CMD; for strobes (DQS, /DQS, DQSL, /DQSL, DQSU, /DQSU) use  
VIH/VIL(AC) of DQs.  
2. VIH(AC)/VIL(AC) for DQs is based on VREFDQ; VIH(AC)/VIL(AC) for address/command is based on  
VREFCA; if a reduced ac-high or ac-low level is used for a signal group, then the reduced level applies  
also here.  
3
These values are not defined, however the single ended components of differential signals CK, /CK, DQS,  
/DQS, DQSL, /DQSL, DQSU, /DQSU need to be within the respective limits (VIH(DC) max, VIL(DC)min)  
for single-ended signals as well as the limitations for overshoot and undershoot. Refer to Overshoot and  
Undershoot specifications.  
To guarantee tight setup and hold times as well as output skew parameters with respect to clock and strobe, each  
cross point voltage of differential input signals (CK, /CK and DQS, /DQS) must meet the requirements in table above.  
The differential input cross point voltage VIX is measured from the actual cross point of true and complement signal  
to the midlevel between of VDD and VSS.  
VDD  
CK, DQS  
VIX  
VDD/2  
VIX  
VIX  
/CK, /DQS  
VSS  
VIX Definition  
[Cross point voltage for differential input signals (CK, DQS)]  
Parameter  
Symbol  
pins  
min.  
max.  
150  
Unit  
mV  
Note  
1
Differential input cross point voltage  
relative to VDD/2  
VIX  
CK, /CK  
150  
175  
175  
150  
mV  
mV  
VIX  
DQS, /DQS 150  
Note: 1. Extended range for VIX is only allowed for clock and if CK and /CK are monotonic, have a single-ended  
swing VSEL/VSEH of at least VDD/2 +/-250 mV, and the differential slew rate of CK - /CK is larger than 3  
V/ ns. Refer to the table of Cross point voltage for differential input signals (CK, DQS) for VSEL and VSEH  
standard values.  
Data Sheet E1375E50 (Ver. 5.0)  
19  
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