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EDJ1116BBSE-8A-F 参数 Datasheet PDF下载

EDJ1116BBSE-8A-F图片预览
型号: EDJ1116BBSE-8A-F
PDF下载: 下载PDF文件 查看货源
内容描述: 1G位DDR3 SDRAM [1G bits DDR3 SDRAM]
分类和应用: 存储内存集成电路动态存储器双倍数据速率
文件页数/大小: 151 页 / 1895 K
品牌: ELPIDA [ ELPIDA MEMORY ]
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EDJ1104BBSE, EDJ1108BBSE, EDJ1116BBSE  
T0  
T3  
T4  
T5  
T6  
T7  
T8  
T9  
T10  
T11  
T12  
T13 T14 T15  
CK  
/CK  
Command*3  
READ  
WRIT  
NOP  
NOP  
tWR  
READ to WRIT Command delay = RL + tCCD/2 + 2tCK WL  
tBL = 4 clocks  
tWTR  
Bank  
Col n  
Bank  
Col b  
Address*4  
tRPRE  
tRPST  
tWPRE  
tWPST  
DQS, /DQS  
DQ*2  
Dout Dout Dout Dout  
n+1 n+2 n+3  
Din Din Din Din  
b+1 b+2 b+3  
n
b
RL = 5  
WL = 5  
VIH or VIL  
Notes: 1. BC4, RL = 5 (CL = 5, AL = 0), WL = 5 (CWL = 5, AL = 0).  
2. Dout n = data-out from column n, Din b= data-in from column b.  
3. NOP commands are shown for ease of illustration; other commands may be valid at these times.  
4. BC4 setting activated by MR0 bit [A1, A0] = [0, 1] and A12 = 0 during READ command at T0 and WRIT command T4.  
READ (BC4) to WRITE (BC4) OTF  
T0  
T4  
T5  
T6  
T7  
T8  
T9  
T10  
T11  
T12  
T13 T14  
CK  
/CK  
Command*3  
READ  
READ  
NOP  
NOP  
tCCD  
Bank  
Col n  
Bank  
Col b  
Address*4  
tRPST  
tRPRE  
DQS, /DQS  
DQ*2  
Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout  
n
n+1 n+2 n+3 n+4 n+5 n+6 n+7  
b
b+1 b+2 b+3  
RL = 5  
RL = 5  
VIH or VIL  
Notes: 1. RL = 5 (CL = 5, AL = 0).  
2. Dout n (or b) = data-out from column n (or column b).  
3. NOP commands are shown for ease of illustration; other commands may be valid at these times.  
4. BC4 setting activated by MR0 bit [A1, A0] = [0, 1] and A12 = 0 during READ command at T4.  
BL8 setting activated by MR0 bit [A1, A0] = [0, 1] and A12 = 1 during READ command at T0.  
READ (BL8) to READ (BC4) OTF  
Data Sheet E1375E50 (Ver. 5.0)  
108  
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