EDE1108AFBG
Write Data Mask
One write data mask (DM) pin for each 8 data bits (DQ) will be supported on DDR2 SDRAMs, Consistent with the
implementation on DDR-I SDRAMs. It has identical timings on write operations as the data bits, and though used in
a uni-directional manner, is internally loaded identically to data bits to insure matched system timing. DM is not used
during read cycles.
T1
T2
T3
T4
T5
Tn
DQS
/DQS
in
DQ
DM
in
in
in
in
in
in
in
in
Write mask latency = 0
Data Mask Timing
[tDQSS(min.)]
/CK
CK
tWR
WRIT
Command
NOP
WL
tDQSS
DQS, /DQS
DQ
in0
in2 in3
DM
WL
tDQSS
[tDQSS(max.)]
DQS, /DQS
DQ
in0
in2 in3
DM
Data Mask Function, WL = 3, AL = 0 shown
Preliminary Data Sheet E1430E20 (Ver. 2.0)
58
ELPIDA [ ELPIDA MEMORY ]
