欢迎访问ic37.com |
会员登录 免费注册
发布采购

EDE1108AFBG-8G-F 参数 Datasheet PDF下载

EDE1108AFBG-8G-F图片预览
型号: EDE1108AFBG-8G-F
PDF下载: 下载PDF文件 查看货源
内容描述: 1G位DDR2 SDRAM [1G bits DDR2 SDRAM]
分类和应用: 存储内存集成电路动态存储器双倍数据速率
文件页数/大小: 78 页 / 734 K
品牌: ELPIDA [ ELPIDA MEMORY ]
 浏览型号EDE1108AFBG-8G-F的Datasheet PDF文件第39页浏览型号EDE1108AFBG-8G-F的Datasheet PDF文件第40页浏览型号EDE1108AFBG-8G-F的Datasheet PDF文件第41页浏览型号EDE1108AFBG-8G-F的Datasheet PDF文件第42页浏览型号EDE1108AFBG-8G-F的Datasheet PDF文件第44页浏览型号EDE1108AFBG-8G-F的Datasheet PDF文件第45页浏览型号EDE1108AFBG-8G-F的Datasheet PDF文件第46页浏览型号EDE1108AFBG-8G-F的Datasheet PDF文件第47页  
EDE1108AFBG  
Extended Mode Register Set for OCD Impedance Adjustment  
OCD impedance adjustment can be done using the following EMRS mode. In drive mode all outputs are driven out  
by DDR2 SDRAM and drive of RDQS is dependent on EMRS bit enabling RDQS operation. In Drive (1) mode, all  
DQ, DQS (and RDQS) signals are driven high and all /DQS signals are driven low. In drive (0) mode, all DQ, DQS  
(and RDQS) signals are driven low and all /DQS signals are driven high.  
In adjust mode, BL = 4 of operation code data must be used. In case of OCD calibration default, output driver  
characteristics follow approximate nominal V/I curve for 18output drivers, but are not guaranteed. If tighter control  
is required, which is controlled within 18Ω ± 3driver impedance range, OCD must be used.  
OCD applies only to normal full strength output drive setting defined by EMRS (1) and if reduced strength is set,  
OCD default output driver characteristics are not applicable. When OCD calibration adjust mode is used, OCD  
default output driver characteristics are not applicable.  
[OCD Mode Set Program]  
A9  
0
A8  
0
A7  
0
Operation  
OCD calibration mode exit  
Drive (1) DQ, DQS, (RDQS) high and /DQS low  
Drive (0) DQ, DQS, (RDQS) low and /DQS high  
Adjust mode  
0
0
1
0
1
0
1
0
0
1
1
1
OCD calibration default  
OCD Impedance Adjustment  
To adjust output driver impedance, controllers must issue the ADJUST EMRS command along with a 4bit burst code  
to DDR2 SDRAM as in OCD Adjustment Program table. For this operation, burst length has to be set to BL = 4 via  
MRS command before activating OCD and controllers must drive this burst code to all DQs at the same time. DT0 in  
OCD Adjustment Program table means all DQ bits at bit time 0, DT1 at bit time 1, and so forth. The driver output  
impedance is adjusted for all DDR2 SDRAM DQs simultaneously and after OCD calibration, all DQs and DQS's of a  
given DDR2 SDRAM will be adjusted to the same driver strength setting. The maximum step count for adjustment is  
16 and when the limit is reached, further increment or decrement code has no effect. The default setting may be any  
step within the 16-step range. When Adjust mode command is issued, AL from previously set value must be  
applied.  
[OCD Adjustment Program]  
4bits burst data inputs to all DQs  
Operation  
DT0  
0
DT1  
0
DT2  
0
DT3  
0
Pull-up driver strength  
NOP  
Pull-down driver strength  
NOP  
0
0
0
1
Increase by 1 step  
Decrease by 1 step  
NOP  
NOP  
0
0
1
0
NOP  
0
1
0
0
Increase by 1 step  
Decrease by 1 step  
Increase by 1 step  
Increase by 1 step  
Decrease by 1 step  
Decrease by 1 step  
1
0
0
0
NOP  
0
1
0
1
Increase by 1 step  
Decrease by 1 step  
Increase by 1 step  
Decrease by 1 step  
Reserved  
0
1
1
0
1
0
0
1
1
0
1
0
Other combinations  
Preliminary Data Sheet E1430E20 (Ver. 2.0)  
43  
 复制成功!