EDE1108AFBG
Current state
/CS
H
L
/RAS /CAS /WE Address
Command
DESL
Operation
Note
Extended Mode
register accessing
×
H
H
H
L
L
L
L
L
L
L
×
H
L
×
×
Nop -> Enter idle after tMRD
Nop -> Enter idle after tMRD
H
H
L
×
NOP
L
BA, CA, A10 (AP)
READ/READA ILLEGAL
WRIT/WRITA ILLEGAL
L
L
BA, CA, A10 (AP)
L
H
H
H
L
H
L
BA, RA
ACT
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
L
BA
PRE
PALL
REF
L
L
A10 (AP)
L
H
H
L
×
L
L
×
SELF
MRS
L
L
BA, MRS-OPCODE
BA, EMRS-OPCODE
L
L
L
EMRS (1) (2) ILLEGAL
Remark: H = VIH. L = VIL. × = VIH or VIL
Notes: 1. This command may be issued for other banks, depending on the state of the banks.
2. All banks must be in "IDLE".
3. All AC timing specs must be met.
4. Only allowed at the boundary of 4 bits burst. Burst interruptions at other timings are illegal.
5. Available in case tRCD is satisfied by AL setting.
6. Available in case tWTR is satisfied.
7. The DDR2 SDRAM supports the concurrent auto-precharge feature, a read with auto-precharge
enabled,or a write with auto-precharge enabled, may be followed by any column command to other
banks, as long as that command does not interrupt the read or write data transfer, and all other related
limitations apply. (E.g. Conflict between READ data and WRITE data must be avoided.)
The minimum delay from a read or write command with auto precharge enabled, to a command to a
different bank, is summarized below.
To command (different bank, non-
interrupting command)
Minimum delay
(Concurrent AP supported)
From command
Read w/AP
Units
tCK
tCK
tCK
tCK
tCK
tCK
Read or Read w/AP
Write or Write w/AP
Precharge or Activate
Read or Read w/AP
Write or Write w/AP
Precharge or Activate
BL/2
(BL/2) + 2
1
Write w/AP
(CL − 1) + (BL/2) + tWTR
BL/2
1
Preliminary Data Sheet E1430E20 (Ver. 2.0)
35
ELPIDA [ ELPIDA MEMORY ]
