EDE1104ABSE, EDE1108ABSE, EDE1116ABSE
Burst Mode Operation
Burst mode operation is used to provide a constant flow of data to memory locations (write cycle), or from memory
locations (read cycle). The parameters that define how the burst mode will operate are burst sequence and burst
length. DDR2 SDRAM supports 4 bits burst and 8bits burst modes only. For 8 bits burst mode, full interleave
address ordering is supported, however, sequential address ordering is nibble based for ease of implementation.
The burst type, either sequential or interleaved, is programmable and defined by the address bit 3 (A3) of the MRS,
which is similar to the DDR-I SDRAM operation. Seamless burst read or write operations are supported.
Unlike DDR-I devices, interruption of a burst read or writes operation is limited to ready by Read or Write by Write at
the boundary of Burst 4. Therefore the burst stop command is not supported on DDR2 SDRAM devices.
[Burst Length and Sequence]
Burst length
Starting address (A2, A1, A0) Sequential addressing (decimal)
Interleave addressing (decimal)
0, 1, 2, 3
000
001
010
011
000
001
010
011
100
101
110
111
0, 1, 2, 3
1, 2, 3, 0
1, 0, 3, 2
4
2, 3, 0, 1
2, 3, 0, 1
3, 0, 1, 2
3, 2, 1, 0
0, 1, 2, 3, 4, 5, 6, 7
1, 2, 3, 0, 5, 6, 7, 4
2, 3, 0, 1, 6, 7, 4, 5
3, 0, 1, 2, 7, 4, 5, 6
4, 5, 6, 7, 0, 1, 2, 3
5, 6, 7, 4, 1, 2, 3, 0
6, 7, 4, 5, 2, 3, 0, 1
7, 4, 5, 6, 3, 0, 1, 2
0, 1, 2, 3, 4, 5, 6, 7
1, 0, 3, 2, 5, 4, 7, 6
2, 3, 0, 1, 6, 7, 4, 5
3, 2, 1, 0, 7, 6, 5, 4
4, 5, 6, 7, 0, 1, 2, 3
5, 4, 7, 6, 1, 0, 3, 2
6, 7, 4, 5, 2, 3, 0, 1
7, 6, 5, 4, 3, 2, 1, 0
8
Note: Page length is a function of I/O organization and column addressing
32M bits × 4 organization (CA0 to CA9, CA11); Page Length = 2048 bits
16M bits × 8 organization (CA0 to CA9); Page Length = 1024 bits
8M bits × 16 organization (CA0 to CA9); Page Length = 1024 bits
Data Sheet E0852E50 (Ver. 5.0)
54
ELPIDA [ ELPIDA MEMORY ]
