EDE1104ABSE, EDE1108ABSE, EDE1116ABSE
DDR2 SDRAM Extended Mode Registers Set [EMRS]
EMRS (1) Programming
The extended mode register (1) stores the data for enabling or disabling the DLL, output driver strength, additive
latency, ODT, /DQS disable, OCD program, RDQS enable. The default value of the extended mode register (1) is
not defined, therefore the extended mode register (1) must be written after power-up for proper operation. The
extended mode register (1) is written by asserting low on /CS, /RAS, /CAS, /WE, high on BA0 and low on BA1, BA2
while controlling the states of address pins A0 to A13. The DDR2 SDRAM should be in all bank precharge with CKE
already high prior to writing into the extended mode register (1). The mode register set command cycle time (tMRD)
must be satisfied to complete the write operation to the extended mode register (1). Mode register contents can be
changed using the same command and clock cycle requirements during normal operation as long as all banks are in
the precharge state. A0 is used for DLL enable or disable. A1 is used for enabling a half strength output driver. A3
to A5 determines the additive latency, A7 to A9 are used for OCD control, A10 is used for /DQS disable and A11 is
used for RDQS enable. A2 and A6 are used for ODT setting.
BA2 BA1 BA0 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Address field
0*1
/DQS OCD program Rtt Additive latency Rtt D.I.C DLL
RDQS
Extended mode register
Qoff
0
0
1
BA2 BA1
BA0
0
MRS mode
MRS
Rtt (nominal )
ODT Disabled
75Ω
A6
0
A2
0
0
0
0
0
0
0
1
1
1
A0
0
DLL enable
Enable
EMRS(1)
0
1
0
EMRS(2)
150Ω
1
0
1
1
Disable
EMRS(3): Reserved
50Ω
1
1
Driver impedance adjustment
Operation
A9
0
A8
0
A7
0
OCD calibration mode exit
Drive(1)
Additive latency
0
0
1
0
1
0
Drive(0)
Adjust mode*2
A5
0
A4
0
A3
0
Latency
1
0
0
0
1
1
1
OCD Calibration default*3
0
0
1
1
0
1
0
2
Qoff*4
A12
0
1
1
3
Output buffers enabled
Output buffers disabled
0
1
1
0
0
4
1
0
1
Reserved
Reserved
Reserved
1
1
0
A10 /DQS enable
1
1
1
0
1
Enable
Disable
Driver strength control
Output driver
impedance control
Normal
Driver
size
A1
0
A11 RDQS enable
100%
60%
0
1
Disable
Enable
1
Weak
Strobe function matrix
A11
A10
(RDQS enable) (/DQS enable)
RDQS/DM /RDQS
DQS
DQS
/DQS
/DQS
0 (Disable)
0 (Disable)
1 (Enable)
1 (Enable)
0 (Enable)
1 (Disable)
0 (Enable)
1 (Disable)
DM
DM
High-Z
High-Z
/RDQS
High-Z
DQS High-Z
DQS /DQS
DQS High-Z
RDQS
RDQS
Notes: 1. A13 are reserved for future use, and must be programmed to 0 when setting the extended mode register.
When adjust mode is issued, AL from previously set value must be applied.
2
3. After setting to default, OCD mode needs to be exited by setting A9 to A7 to 000.
Refer to the chapter Off-Chip Driver (OCD)Impedance Adjustment for detailed information.
4. Output disabled - DQ, DQS, /DQS, RDQS, /RDQS. This feature is used in conjunction with DIMM
IDD measurements when IDDQ is not desired to be included.
EMRS (1)
Data Sheet E0852E50 (Ver. 5.0)
43
ELPIDA [ ELPIDA MEMORY ]
