EDE1104ABSE, EDE1108ABSE, EDE1116ABSE
8. The minimum delay from the read, write and precharge command to the precharge command to the same
bank is summarized below.
[Precharge and Auto Precharge Clarification]
Minimum delay between “From
From command
Read
To command
command” to “To Command“
AL + (BL/2) + Max.(RTP, 2) − 2
AL + (BL/2) + Max.(RTP, 2) − 2
Units
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
Notes
a, b
a, b
a, b
a, b
b
Precharge (to same bank as read)
Precharge all
Read w/AP
Write
Precharge (to same bank as read w/AP) AL + (BL/2) + Max.(RTP, 2) − 2
Precharge all
AL + (BL/2) + Max.(RTP, 2) − 2
WL + (BL/2) + tWR
Precharge (to same bank as write)
Precharge all
WL + (BL/2) + tWR
b
Write w/AP
Precharge
Precharge all
Precharge (to same bank as write w/AP) WL + (BL/2) + WR
b
Precharge all
WL + (BL/2) + WR
b
Precharge (to same bank as precharge)
Precharge all
1
1
1
1
b
b
Precharge
b
Precharge all
b
a. RTP[cycles] = RU{ tRTP[ns] / tCK[ns] }, where RU stands for round up.
tCK(avg) should be used in place of tCK for DDR2-667/800.
b. For a given bank, the precharge period should be counted from the latest precharge command, either one
bank precharge or precharge all, issued to that bank. The precharge period is satisfied after tRP
depending on the latest precharge command issued to that bank.
Data Sheet E0852E50 (Ver. 5.0)
39
ELPIDA [ ELPIDA MEMORY ]
