EDD5104ADTA-E, EDD5108ADTA-E, EDD5116ADTA-E
Pin Capacitance (TA = +25°C, VDD, VDDQ = 2.5V ± 0.2V)
Parameter
Symbol
CI1
Pins
min.
2.0
2.0
—
typ
—
—
—
—
—
—
max.
3.0
3.0
0.25
0.5
5
Unit
pF
pF
pF
pF
pF
pF
Notes
Input capacitance
CK, /CK
1
CI2
All other input pins
CK, /CK
1
Delta input capacitance
Cdi1
Cdi2
CI/O
Cdio
1
All other input-only pins
DQ, DM, DQS
DQ, DM, DQS
—
1
Data input/output capacitance
Delta input/output capacitance
4.0
—
1, 2,
1
0.5
Notes: 1. These parameters are measured on conditions: f = 100MHz, VOUT = VDDQ/2, ∆VOUT = 0.2V,
TA = +25°C.
2. DOUT circuits are disabled.
AC Characteristics (TA = 0 to +70°C, VDD, VDDQ = 2.5V ± 0.2V, VSS, VSSQ = 0V)
-6B
-7A
-7B
min.
max.
12
min.
max
12
min.
max.
12
Parameter
Clock cycle time
(CL = 2)
Symbol
tCK
Unit Notes
7.5
7.5
10
ns
10
(CL = 2.5)
tCK
tCH
tCL
6
12
7.5
12
7.5
12
ns
CK high-level width
CK low-level width
0.45
0.45
0.55
0.55
0.45
0.45
0.55
0.55
0.45
0.45
0.55
0.55
tCK
tCK
min
min
min
CK half period
tHP
—
—
—
tCK
ns
(tCH, tCL)
(tCH, tCL)
(tCH, tCL)
DQ output access time from CK, /CK tAC
DQS output access time from CK,
/CK
–0.7
0.7
0.6
0.45
–0.75
–0.75
—
0.75
0.75
0.5
–0.75
–0.75
—
0.75
0.75
0.5
2, 11
2, 11
3
tDQSCK –0.6
ns
DQS to DQ skew
tDQSQ
—
ns
ns
ns
DQ/DQS output hold time from DQS tQH
tHP – tQHS —
tHP – tQHS —
tHP – tQHS —
Data hold skew factor
tQHS
—
0.55
—
0.75
—
0.75
Data-out high-impedance time from
tHZ
tLZ
–0.7
0.7
0.7
–0.75
0.75
0.75
–0.75
0.75
0.75
ns
ns
5, 11
6, 11
CK, /CK
Data-out low-impedance time from
CK, /CK
–0.7
–0.75
–0.75
Read preamble
tRPRE
tRPST
tDS
0.9
1.1
0.6
—
0.9
0.4
0.5
0.5
1.75
0
1.1
0.6
—
0.9
0.4
0.5
0.5
1.75
0
1.1
0.6
—
tCK
tCK
ns
Read postamble
0.4
DQ and DM input setup time
DQ and DM input hold time
DQ and DM input pulse width
Write preamble setup time
Write preamble
0.45
0.45
1.75
8
8
7
tDH
—
—
—
ns
tDIPW
—
—
—
ns
tWPRES 0
—
—
—
ns
tWPRE 0.25
tWPST 0.4
—
0.25
0.4
—
0.25
0.4
—
tCK
tCK
Write postamble
0.6
0.6
0.6
9
Write command to first DQS latching
transition
tDQSS
0.75
1.25
0.75
1.25
0.75
1.25
tCK
DQS falling edge to CK setup time
tDSS
0.2
—
—
—
0.2
—
—
—
—
0.2
—
—
—
—
tCK
tCK
tCK
tCK
DQS falling edge hold time from CK tDSH
0.2
0.2
0.2
DQS input high pulse width
DQS input low pulse width
tDQSH
tDQSL
0.35
0.35
0.35
0.35
0.35
0.35
Address and control input setup time tIS
Address and control input hold time tIH
0.75
0.75
—
—
0.9
0.9
—
—
0.9
0.9
—
—
ns
ns
8
8
Preliminary Data Sheet E0501E10 (Ver. 1.0)
6
ELPIDA [ ELPIDA MEMORY ]
