EDD5104ABTA, EDD5108ABTA
Timing Parameter Measured in Clock Cycle
Number of clock cycle
tCK
6ns
7.5ns
Parameter
Symbol
tWPD
tRPD
min.
max.
min.
max.
Write to pre-charge command delay (same bank)
Read to pre-charge command delay (same bank)
Write to read command delay (to input all data)
4 + BL/2
BL/2
3 + BL/2
BL/2
tWRD
2 + BL/2
2 + BL/2
Burst stop command to write command delay
(CL = 2)
(CL = 2.5)
Burst stop command to DQ High-Z
(CL = 2)
(CL = 2.5)
tBSTW
tBSTW
tBSTZ
tBSTZ
2
2
3
3
2
2
2
2
2.5
2.5
2.5
2.5
Read command to write command delay
(to output all data)
(CL = 2)
tRWD
2 + BL/2
2 + BL/2
(CL = 2.5)
Pre-charge command to High-Z
(CL = 2)
tRWD
tHZP
3 + BL/2
2
3 + BL/2
2
2
2
(CL = 2.5)
tHZP
2.5
1
2.5
1
2.5
1
2.5
1
Write command to data in latency
Write recovery time
tWCD
tWR
3
2
DM to data in latency
tDMD
tMRD
tSNR
tSRD
tPDEN
tPDEX
0
0
0
0
Mode register set command cycle time
Self refresh exit to non-read command
Self refresh exit to read command
Power down entry
2
2
12
200
1
10
200
1
1
1
Power down exit to command input
1
1
Preliminary Data Sheet E0237E30 (Ver. 3.0)
9
ELPIDA [ ELPIDA MEMORY ]
