EDD5104ABTA, EDD5108ABTA
-6B
-7A
-7B
min.
max.
—
min.
0.9
0.9
2.2
max
—
min.
max.
—
Parameter
Symbol
Unit
Notes
Address and control input setup time tIS
0.75
0.75
2.2
0.9
0.9
2.2
Address and control input hold time tIH
Address and control input pulse
width
—
—
—
ns
ns
8
7
tIPW
—
—
—
Mode register set command cycle
tMRD
tRAS
tRC
2
—
2
—
2
—
tCK
time
Active to Precharge command
period
Active to Active/Auto refresh
command period
Auto refresh to Active/Auto refresh
command period
Active to Read/Write delay
42
60
72
120000 45
120000 45
120000 ns
—
—
67.5
—
—
67.5
—
—
ns
ns
tRFC
tRCD
75
75
18
—
—
—
—
—
20
—
—
—
—
—
20
—
—
—
—
—
ns
ns
ns
ns
ns
Precharge to active command period tRP
18
20
20
Active to Autoprecharge delay
Active to active command period
Write recovery time
tRAP
tRCD min.
tRCD min.
tRCD min.
tRRD
tWR
12
15
15
15
15
15
Auto precharge write recovery and
precharge time
(tWR/tCK)+
(tRP/tCK)
(tWR/tCK)+
(tRP/tCK)
(tWR/tCK)+
(tRP/tCK)
tDAL
—
—
tCK
13
Internal write to Read command
delay
Average periodic refresh interval
tWTR
tREF
1
—
1
—
1
—
tCK
µs
—
7.8
—
7.8
—
7.8
Notes: 1. On all AC measurements, we assume the test conditions shown in the next page. For timing parameter
definitions, see ‘Timing Waveforms’ section.
2. This parameter defines the signal transition delay from the cross point of CK and /CK. The signal
transition is defined to occur when the signal level crossing VTT.
3. The timing reference level is VTT.
4. Output valid window is defined to be the period between two successive transition of data out or DQS
(read) signals. The signal transition is defined to occur when the signal level crossing VTT.
5. tHZ is defined as DOUT transition delay from Low-Z to High-Z at the end of read burst operation. The
timing reference is cross point of CK and /CK. This parameter is not referred to a specific DOUT voltage
level, but specify when the device output stops driving.
6. tLZ is defined as DOUT transition delay from High-Z to Low-Z at the beginning of read operation. This
parameter is not referred to a specific DOUT voltage level, but specify when the device output begins
driving.
7. Input valid windows is defined to be the period between two successive transition of data input or DQS
(write) signals. The signal transition is defined to occur when the signal level crossing VREF.
8. The timing reference level is VREF.
9. The transition from Low-Z to High-Z is defined to occur when the device output stops driving. A specific
reference voltage to judge this transition is not given.
10. tCK (max.) is determined by the lock range of the DLL. Beyond this lock range, the DLL operation is not
assured.
11. tCK = tCK (min.) when these parameters are measured. Otherwise, absolute minimum values of these
values are 10% of tCK.
12. VDD is assumed to be 2.5V ± 0.2V. VDD power supply variation per cycle expected to be less than
0.4V/400 cycle.
13. tDAL = (tWR/tCK)+(tRP/tCK)
For each of the terms above, if not already an integer, round to the next highest integer.
Example: For –7A Speed at CL = 2.5, tCK = 7.5ns, tWR = 15ns and tRP= 20ns,
tDAL = (15ns/7.5ns) + (20ns/7.5ns) = (2) + (3)
tDAL = 5 clocks
Preliminary Data Sheet E0237E30 (Ver. 3.0)
7
ELPIDA [ ELPIDA MEMORY ]
