EDD5104ABTA, EDD5108ABTA
A Write command to the consecutive Precharge command interval (same bank)
The minimum interval tWPD ((BL/2 + 3 for tCK = 7.5 ns, BL/2 + 4 for tCK = 6 ns) cycles) is necessary between the
write command and the precharge command.
t0
t1
t2
t3
t4
t5
t6
t7
CK
/CK
Command
PRE/PALL
WRIT
NOP
tWPD
NOP
tWR
DM
DQS
DQ
in0
in1
in2
in3
Last data input
WRITE to PRECHARGE Command Interval (same bank) (BL = 4)
Precharge Termination in Write Cycles
During a burst write cycle without auto precharge, the burst write operation is terminated by a precharge command
of the same bank. In order to write the last input data, tWR (min) must be satisfied. When the precharge command
is issued, the invalid data must be masked by DM.
t0
t1
t2
t3
t4
t5
t6
t7
CK
/CK
Command
PRE/PALL
WRIT
NOP
NOP
tWR
DM
DQS
DQ
in0
in1
in2
in3
Data masked
Precharge Termination in Write Cycles (same bank) (BL = 4)
Preliminary Data Sheet E0237E30 (Ver. 3.0)
38
ELPIDA [ ELPIDA MEMORY ]
