EDD5104ABTA, EDD5108ABTA
t0
t1
t2
t3
t4
t5
t6
t7
t8
CK
/CK
Command
WRIT
NOP
READ
NOP
2 cycle
CL=2
DM
High-Z
DQ
in0 in1
in2
in3
out0 out1 out2 out3
High-Z
DQS
Data masked
BL = 4
CL= 2
[WRITE to READ delay = 2 clock cycle]
t0
t1
t2
t3
t4
t5
t6
t7
t8
CK
/CK
Command
WRIT
NOP
3 cycle
READ
NOP
CL=2
tWTR*
DM
out0 out1 out2 out3
DQ
in0 in1
in2
in3
DQS
BL = 4
CL= 2
Data masked
Note: tWTR is referenced from the first positive CK edge after the last desired data in pair tWTR.
[WRITE to READ delay = 3 clock cycle]
Preliminary Data Sheet E0237E30 (Ver. 3.0)
35