Interleaved Column Write Cycle (2/2) (Burst Length = 8, /CAS Latency = 2.5)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
T23
CLK
/CLK
CKE
/CS
H
/RAS
/CAS
/WE
BA0
BA1
A10
ADD
RAa
RAa
RBa
RBa
CAa
CBa
CBb
CAb
CBd
CBc
DQM
DQS
DQ
Hi-Z
Hi-Z
V
TT
V
TT
Aa1
Aa2
Aa3
Aa4
Aa5
Aa6
Aa7
Aa8
Ba1
Ba2
Ba3
Ba4
Bb1
Bb2
Bb3
Bb4
Bc1
Bc2
Bc3
Bc4
Ab1
Ab2
Bd5
Bd6
Bd7
Bd8
Ab3
Ab4
Bd1
Bd2
Bd3
Bd4
Activate
Write
Write
Write
Write
Write
Write
Command
for Bank A
Command
for Bank A
Command
for Bank B
Command
for Bank B
Command
for Bank B
Command
for Bank A
Command
for Bank B
Activate
Command
for Bank B
Precharge
Command
for Bank A
Precharge
Command
for Bank B