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EBJ21RE8BAFA-8C-E 参数 Datasheet PDF下载

EBJ21RE8BAFA-8C-E图片预览
型号: EBJ21RE8BAFA-8C-E
PDF下载: 下载PDF文件 查看货源
内容描述: 注册2GB DDR3 SDRAM DIMM [2GB Registered DDR3 SDRAM DIMM]
分类和应用: 动态存储器双倍数据速率
文件页数/大小: 20 页 / 216 K
品牌: ELPIDA [ ELPIDA MEMORY ]
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EBJ21RE8BAFA  
CKE (input pin)  
CKE high activates, and CKE low deactivates, internal clock signals and device input buffers and output drivers.  
Taking CKE low provides precharge power-down and self-refresh operation (all banks idle), or active power-down  
(row active in any bank). CKE is asynchronous for self-refresh exit. After VREF has become stable during the  
power-on and initialization sequence, it must be maintained for proper operation of the CKE receiver. For proper  
self-refresh entry and exit, VREF must be maintained to this input. CKE must be maintained high throughout read  
and write accesses. Input buffers, excluding CK, /CK, ODT and CKE are disabled during power-down. Input buffers,  
excluding CKE, are disabled during self-refresh.  
DQ and CB (input and output pins)  
Bi-directional data bus.  
DQS and /DQS (input and output pin)  
Output with read data, input with write data. Edge-aligned with read data, centered in write data.  
The data strobe DQS is paired with differential signals /DQS to provide differential pair signaling to the system during  
READs and WRITEs.  
ODT (input pins)  
ODT (registered high) enables termination resistance internal to the DDR3 SDRAM. When enabled, ODT is only  
applied to each DQ, DQS, /DQS, DM. The ODT pin will be ignored if the mode register (MR1) is programmed to  
disable ODT.  
DM (input pins)  
DM is an input mask signal for write data. Input data is masked when DM is sampled high coincident with that input  
data during a write access. DM is sampled on both edges of DQS. For ×8 configuration, the function of DM or  
TDQS, /TDQS is enabled by mode register A11 setting in MR1.  
TDQS, /TDQS (output pins)  
TDQS and /TDQS is applicable for ×8 configuration only. When enabled via mode register A11 = 1 in MR1, DRAM  
will enable the same termination resistance function on TDQS, /TDQS that is applied to DQS, /DQS. When disabled  
via mode register A11 = 0 in MR1, DM/TDQS will provide the data mask function and /TDQS is not used. ×4/×16  
configuration must be disabled the TDQS function via mode register A11 = 0 in MR1.  
VDD (power supply pins)  
1.5V is applied. (VDD is for the internal circuit.)  
VDDSPD (power supply pin)  
3.3V is applied (For serial EEPROM).  
VSS (power supply pin)  
Ground is connected.  
VTT (power supply pin)  
Termination supply.  
VREFDQ (power supply)  
Reference voltage for DQ.  
VREFCA (power supply)  
Reference voltage for CA.  
SCL (input pin)  
Clock input for serial PD.  
Data Sheet E1251E40 (Ver. 4.0)  
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